2018-12-20 12:33:42 +09:00
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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2017-06-23 17:11:07 +09:00
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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2019-08-02 16:39:59 +09:00
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#include <clk.h>
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#include <debug_uart.h>
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2017-06-23 17:11:07 +09:00
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#include <dm.h>
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2019-08-02 16:39:59 +09:00
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#include <dt-structs.h>
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2020-05-11 02:40:02 +09:00
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#include <init.h>
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2017-06-23 17:11:07 +09:00
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#include <ram.h>
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2019-08-02 16:39:59 +09:00
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#include <regmap.h>
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2017-06-23 17:11:07 +09:00
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#include <syscon.h>
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2019-08-02 16:39:59 +09:00
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#include <asm/io.h>
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2019-03-28 12:01:23 +09:00
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#include <asm/arch-rockchip/clock.h>
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2019-08-02 16:39:59 +09:00
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#include <asm/arch-rockchip/cru_rk3328.h>
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2019-03-28 12:01:23 +09:00
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#include <asm/arch-rockchip/grf_rk3328.h>
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2019-11-15 12:04:33 +09:00
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#include <asm/arch-rockchip/sdram.h>
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2019-08-02 16:39:59 +09:00
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#include <asm/arch-rockchip/sdram_rk3328.h>
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#include <asm/arch-rockchip/uart.h>
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2017-06-23 17:11:07 +09:00
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struct dram_info {
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2019-08-02 16:39:59 +09:00
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#ifdef CONFIG_TPL_BUILD
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2019-11-15 12:04:44 +09:00
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struct ddr_pctl_regs *pctl;
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struct ddr_phy_regs *phy;
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2019-08-02 16:39:59 +09:00
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struct clk ddr_clk;
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struct rk3328_cru *cru;
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2019-11-15 12:04:44 +09:00
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struct msch_regs *msch;
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2019-08-02 16:39:59 +09:00
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struct rk3328_ddr_grf_regs *ddr_grf;
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#endif
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2017-06-23 17:11:07 +09:00
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struct ram_info info;
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struct rk3328_grf_regs *grf;
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};
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2019-08-02 16:39:59 +09:00
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#ifdef CONFIG_TPL_BUILD
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struct rk3328_sdram_channel sdram_ch;
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struct rockchip_dmc_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3328_dmc dtplat;
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#else
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struct rk3328_sdram_params sdram_params;
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#endif
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struct regmap *map;
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};
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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static int conv_of_platdata(struct udevice *dev)
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{
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struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
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struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
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int ret;
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ret = regmap_init_mem_platdata(dev, dtplat->reg,
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ARRAY_SIZE(dtplat->reg) / 2,
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&plat->map);
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if (ret)
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return ret;
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return 0;
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}
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#endif
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static void rkclk_ddr_reset(struct dram_info *dram,
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u32 ctl_srstn, u32 ctl_psrstn,
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u32 phy_srstn, u32 phy_psrstn)
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{
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writel(ddrctrl_srstn_req(ctl_srstn) | ddrctrl_psrstn_req(ctl_psrstn) |
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ddrphy_srstn_req(phy_srstn) | ddrphy_psrstn_req(phy_psrstn),
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&dram->cru->softrst_con[5]);
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writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]);
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}
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2019-11-15 12:04:44 +09:00
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static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz)
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2019-08-02 16:39:59 +09:00
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{
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unsigned int refdiv, postdiv1, postdiv2, fbdiv;
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int delay = 1000;
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2019-11-15 12:04:44 +09:00
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u32 mhz = hz / MHZ;
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2019-08-02 16:39:59 +09:00
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refdiv = 1;
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if (mhz <= 300) {
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postdiv1 = 4;
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postdiv2 = 2;
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} else if (mhz <= 400) {
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postdiv1 = 6;
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postdiv2 = 1;
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} else if (mhz <= 600) {
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postdiv1 = 4;
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postdiv2 = 1;
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} else if (mhz <= 800) {
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postdiv1 = 3;
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postdiv2 = 1;
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} else if (mhz <= 1600) {
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postdiv1 = 2;
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postdiv2 = 1;
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} else {
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postdiv1 = 1;
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postdiv2 = 1;
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}
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fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24;
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writel(((0x1 << 4) << 16) | (0 << 4), &dram->cru->mode_con);
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writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]);
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writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv),
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&dram->cru->dpll_con[1]);
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while (delay > 0) {
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udelay(1);
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if (LOCK(readl(&dram->cru->dpll_con[1])))
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break;
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delay--;
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}
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writel(((0x1 << 4) << 16) | (1 << 4), &dram->cru->mode_con);
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}
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static void rkclk_configure_ddr(struct dram_info *dram,
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struct rk3328_sdram_params *sdram_params)
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{
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void __iomem *phy_base = dram->phy;
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/* choose DPLL for ddr clk source */
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clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7);
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/* for inno ddr phy need 2*freq */
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2019-11-15 12:04:44 +09:00
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rkclk_set_dpll(dram, sdram_params->base.ddr_freq * MHZ * 2);
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2019-08-02 16:39:59 +09:00
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}
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/* return ddrconfig value
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* (-1), find ddrconfig fail
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* other, the ddrconfig value
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* only support cs0_row >= cs1_row
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*/
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2019-11-15 12:04:44 +09:00
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static u32 calculate_ddrconfig(struct rk3328_sdram_params *sdram_params)
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2019-08-02 16:39:59 +09:00
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{
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2019-11-15 12:04:44 +09:00
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struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
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2019-08-02 16:39:59 +09:00
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u32 cs, bw, die_bw, col, row, bank;
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2019-11-15 12:04:44 +09:00
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u32 cs1_row;
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2019-08-02 16:39:59 +09:00
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u32 i, tmp;
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u32 ddrconf = -1;
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2019-11-15 12:04:44 +09:00
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cs = cap_info->rank;
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bw = cap_info->bw;
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die_bw = cap_info->dbw;
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col = cap_info->col;
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row = cap_info->cs0_row;
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cs1_row = cap_info->cs1_row;
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bank = cap_info->bk;
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if (sdram_params->base.dramtype == DDR4) {
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/* when DDR_TEST, CS always at MSB position for easy test */
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if (cs == 2 && row == cs1_row) {
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/* include 2cs cap both 2^n or both (2^n - 2^(n-2)) */
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tmp = ((row - 13) << 3) | (1 << 2) | (bw & 0x2) |
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die_bw;
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for (i = 17; i < 21; i++) {
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if (((tmp & 0x7) ==
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(ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
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((tmp & 0x3c) <=
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(ddr4_cfg_2_rbc[i - 10] & 0x3c))) {
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ddrconf = i;
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goto out;
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}
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}
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}
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2019-08-02 16:39:59 +09:00
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tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw;
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for (i = 10; i < 17; i++) {
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if (((tmp & 0x7) == (ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
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((tmp & 0x3c) <= (ddr4_cfg_2_rbc[i - 10] & 0x3c)) &&
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((tmp & 0x40) <= (ddr4_cfg_2_rbc[i - 10] & 0x40))) {
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ddrconf = i;
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goto out;
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}
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}
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} else {
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if (bank == 2) {
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ddrconf = 8;
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goto out;
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}
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2019-11-15 12:04:44 +09:00
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/* when DDR_TEST, CS always at MSB position for easy test */
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if (cs == 2 && row == cs1_row) {
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/* include 2cs cap both 2^n or both (2^n - 2^(n-2)) */
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for (i = 5; i < 8; i++) {
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if ((bw + col - 11) == (ddr_cfg_2_rbc[i] &
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0x3)) {
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ddrconf = i;
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goto out;
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}
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}
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}
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2019-08-02 16:39:59 +09:00
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tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0);
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for (i = 0; i < 5; i++)
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if (((tmp & 0xf) == (ddr_cfg_2_rbc[i] & 0xf)) &&
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((tmp & 0x30) <= (ddr_cfg_2_rbc[i] & 0x30))) {
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ddrconf = i;
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goto out;
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}
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}
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out:
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if (ddrconf > 20)
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2019-11-15 12:04:44 +09:00
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printf("calculate ddrconfig error\n");
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2019-08-02 16:39:59 +09:00
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return ddrconf;
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}
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/*******
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* calculate controller dram address map, and setting to register.
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* argument sdram_ch.ddrconf must be right value before
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* call this function.
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*******/
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static void set_ctl_address_map(struct dram_info *dram,
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struct rk3328_sdram_params *sdram_params)
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{
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2019-11-15 12:04:44 +09:00
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struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
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2019-08-02 16:39:59 +09:00
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void __iomem *pctl_base = dram->pctl;
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2019-11-15 12:04:44 +09:00
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sdram_copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0),
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&addrmap[cap_info->ddrconfig][0], 9 * 4);
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if (sdram_params->base.dramtype == LPDDR3 && cap_info->row_3_4)
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2019-08-02 16:39:59 +09:00
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setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31);
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2019-11-15 12:04:44 +09:00
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if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1)
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2019-08-02 16:39:59 +09:00
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setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8);
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2019-11-15 12:04:44 +09:00
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if (cap_info->rank == 1)
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2019-08-02 16:39:59 +09:00
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clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f);
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}
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static int data_training(struct dram_info *dram, u32 cs, u32 dramtype)
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{
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void __iomem *pctl_base = dram->pctl;
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u32 dis_auto_zq = 0;
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2019-11-15 12:04:44 +09:00
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u32 pwrctl;
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u32 ret;
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2019-08-02 16:39:59 +09:00
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2019-11-15 12:04:44 +09:00
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/* disable auto low-power */
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pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL);
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writel(0, pctl_base + DDR_PCTL2_PWRCTL);
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2019-08-02 16:39:59 +09:00
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2019-11-15 12:04:44 +09:00
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dis_auto_zq = pctl_dis_zqcs_aref(dram->pctl);
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2019-08-02 16:39:59 +09:00
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2019-11-15 12:04:44 +09:00
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ret = phy_data_training(dram->phy, cs, dramtype);
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2019-08-02 16:39:59 +09:00
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2019-11-15 12:04:44 +09:00
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pctl_rest_zqcs_aref(dram->pctl, dis_auto_zq);
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2019-08-02 16:39:59 +09:00
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2019-11-15 12:04:44 +09:00
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/* restore auto low-power */
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writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL);
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2019-08-02 16:39:59 +09:00
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2019-11-15 12:04:44 +09:00
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return ret;
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}
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2019-08-02 16:39:59 +09:00
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static void rx_deskew_switch_adjust(struct dram_info *dram)
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{
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u32 i, deskew_val;
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u32 gate_val = 0;
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void __iomem *phy_base = dram->phy;
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for (i = 0; i < 4; i++)
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2019-11-15 12:04:44 +09:00
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gate_val = MAX(readl(PHY_REG(phy_base, 0xfb + i)), gate_val);
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2019-08-02 16:39:59 +09:00
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deskew_val = (gate_val >> 3) + 1;
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deskew_val = (deskew_val > 0x1f) ? 0x1f : deskew_val;
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clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2);
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clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4,
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(deskew_val & 0x1c) << 2);
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}
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static void tx_deskew_switch_adjust(struct dram_info *dram)
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{
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void __iomem *phy_base = dram->phy;
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clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1);
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}
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static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig)
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{
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writel(ddrconfig, &dram->msch->ddrconf);
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}
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2019-11-15 12:04:44 +09:00
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static void sdram_msch_config(struct msch_regs *msch,
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struct sdram_msch_timings *noc_timings)
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{
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writel(noc_timings->ddrtiming.d32, &msch->ddrtiming);
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writel(noc_timings->ddrmode.d32, &msch->ddrmode);
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writel(noc_timings->readlatency, &msch->readlatency);
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writel(noc_timings->activate.d32, &msch->activate);
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writel(noc_timings->devtodev.d32, &msch->devtodev);
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writel(noc_timings->ddr4timing.d32, &msch->ddr4_timing);
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writel(noc_timings->agingx0, &msch->aging0);
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writel(noc_timings->agingx0, &msch->aging1);
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|
|
writel(noc_timings->agingx0, &msch->aging2);
|
|
|
|
writel(noc_timings->agingx0, &msch->aging3);
|
|
|
|
writel(noc_timings->agingx0, &msch->aging4);
|
|
|
|
writel(noc_timings->agingx0, &msch->aging5);
|
|
|
|
}
|
|
|
|
|
2019-08-02 16:39:59 +09:00
|
|
|
static void dram_all_config(struct dram_info *dram,
|
|
|
|
struct rk3328_sdram_params *sdram_params)
|
|
|
|
{
|
2019-11-15 12:04:44 +09:00
|
|
|
struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
|
|
|
|
u32 sys_reg2 = 0;
|
|
|
|
u32 sys_reg3 = 0;
|
|
|
|
|
|
|
|
set_ddrconfig(dram, cap_info->ddrconfig);
|
|
|
|
sdram_org_config(cap_info, &sdram_params->base, &sys_reg2,
|
|
|
|
&sys_reg3, 0);
|
|
|
|
writel(sys_reg2, &dram->grf->os_reg[2]);
|
|
|
|
writel(sys_reg3, &dram->grf->os_reg[3]);
|
|
|
|
|
|
|
|
sdram_msch_config(dram->msch, &sdram_ch.noc_timings);
|
2019-08-02 16:39:59 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static void enable_low_power(struct dram_info *dram,
|
|
|
|
struct rk3328_sdram_params *sdram_params)
|
|
|
|
{
|
|
|
|
void __iomem *pctl_base = dram->pctl;
|
|
|
|
|
|
|
|
/* enable upctl2 axi clock auto gating */
|
|
|
|
writel(0x00800000, &dram->ddr_grf->ddr_grf_con[0]);
|
|
|
|
writel(0x20012001, &dram->ddr_grf->ddr_grf_con[2]);
|
|
|
|
/* enable upctl2 core clock auto gating */
|
|
|
|
writel(0x001e001a, &dram->ddr_grf->ddr_grf_con[2]);
|
|
|
|
/* enable sr, pd */
|
|
|
|
if (PD_IDLE == 0)
|
|
|
|
clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
|
|
|
|
else
|
|
|
|
setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
|
|
|
|
if (SR_IDLE == 0)
|
|
|
|
clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
|
|
|
|
else
|
|
|
|
setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
|
|
|
|
setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sdram_init(struct dram_info *dram,
|
|
|
|
struct rk3328_sdram_params *sdram_params, u32 pre_init)
|
|
|
|
{
|
2019-11-15 12:04:44 +09:00
|
|
|
struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
|
2019-08-02 16:39:59 +09:00
|
|
|
void __iomem *pctl_base = dram->pctl;
|
|
|
|
|
|
|
|
rkclk_ddr_reset(dram, 1, 1, 1, 1);
|
|
|
|
udelay(10);
|
|
|
|
/*
|
|
|
|
* dereset ddr phy psrstn to config pll,
|
|
|
|
* if using phy pll psrstn must be dereset
|
|
|
|
* before config pll
|
|
|
|
*/
|
|
|
|
rkclk_ddr_reset(dram, 1, 1, 1, 0);
|
|
|
|
rkclk_configure_ddr(dram, sdram_params);
|
2019-11-15 12:04:44 +09:00
|
|
|
|
2019-08-02 16:39:59 +09:00
|
|
|
/* release phy srst to provide clk to ctrl */
|
|
|
|
rkclk_ddr_reset(dram, 1, 1, 0, 0);
|
|
|
|
udelay(10);
|
2019-11-15 12:04:44 +09:00
|
|
|
phy_soft_reset(dram->phy);
|
2019-08-02 16:39:59 +09:00
|
|
|
/* release ctrl presetn, and config ctl registers */
|
|
|
|
rkclk_ddr_reset(dram, 1, 0, 0, 0);
|
2019-11-15 12:04:44 +09:00
|
|
|
pctl_cfg(dram->pctl, &sdram_params->pctl_regs, SR_IDLE, PD_IDLE);
|
|
|
|
cap_info->ddrconfig = calculate_ddrconfig(sdram_params);
|
2019-08-02 16:39:59 +09:00
|
|
|
set_ctl_address_map(dram, sdram_params);
|
2019-11-15 12:04:44 +09:00
|
|
|
phy_cfg(dram->phy, &sdram_params->phy_regs, &sdram_params->skew,
|
|
|
|
&sdram_params->base, cap_info->bw);
|
2019-08-02 16:39:59 +09:00
|
|
|
|
|
|
|
/* enable dfi_init_start to init phy after ctl srstn deassert */
|
|
|
|
setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4));
|
|
|
|
rkclk_ddr_reset(dram, 0, 0, 0, 0);
|
|
|
|
/* wait for dfi_init_done and dram init complete */
|
|
|
|
while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* do ddr gate training */
|
2019-11-15 12:04:44 +09:00
|
|
|
if (data_training(dram, 0, sdram_params->base.dramtype) != 0) {
|
|
|
|
printf("data training error\n");
|
|
|
|
return -1;
|
|
|
|
}
|
2019-08-02 16:39:59 +09:00
|
|
|
|
2019-11-15 12:04:44 +09:00
|
|
|
if (sdram_params->base.dramtype == DDR4)
|
|
|
|
pctl_write_vrefdq(dram->pctl, 0x3, 5670,
|
|
|
|
sdram_params->base.dramtype);
|
2019-08-02 16:39:59 +09:00
|
|
|
|
2020-01-07 16:15:20 +09:00
|
|
|
if (pre_init != 0) {
|
2019-08-02 16:39:59 +09:00
|
|
|
rx_deskew_switch_adjust(dram);
|
|
|
|
tx_deskew_switch_adjust(dram);
|
|
|
|
}
|
|
|
|
|
|
|
|
dram_all_config(dram, sdram_params);
|
|
|
|
enable_low_power(dram, sdram_params);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u64 dram_detect_cap(struct dram_info *dram,
|
|
|
|
struct rk3328_sdram_params *sdram_params,
|
|
|
|
unsigned char channel)
|
|
|
|
{
|
2019-11-15 12:04:44 +09:00
|
|
|
struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
|
2019-08-02 16:39:59 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* for ddr3: ddrconf = 3
|
|
|
|
* for ddr4: ddrconf = 12
|
|
|
|
* for lpddr3: ddrconf = 3
|
|
|
|
* default bw = 1
|
|
|
|
*/
|
|
|
|
u32 bk, bktmp;
|
|
|
|
u32 col, coltmp;
|
2019-11-15 12:04:44 +09:00
|
|
|
u32 rowtmp;
|
2019-08-02 16:39:59 +09:00
|
|
|
u32 cs;
|
|
|
|
u32 bw = 1;
|
2019-11-15 12:04:44 +09:00
|
|
|
u32 dram_type = sdram_params->base.dramtype;
|
2019-08-02 16:39:59 +09:00
|
|
|
|
|
|
|
if (dram_type != DDR4) {
|
|
|
|
/* detect col and bk for ddr3/lpddr3 */
|
|
|
|
coltmp = 12;
|
|
|
|
bktmp = 3;
|
|
|
|
rowtmp = 16;
|
|
|
|
|
2019-11-15 12:04:44 +09:00
|
|
|
if (sdram_detect_col(cap_info, coltmp) != 0)
|
2019-08-02 16:39:59 +09:00
|
|
|
goto cap_err;
|
2019-11-15 12:04:44 +09:00
|
|
|
sdram_detect_bank(cap_info, coltmp, bktmp);
|
|
|
|
sdram_detect_dbw(cap_info, dram_type);
|
2019-08-02 16:39:59 +09:00
|
|
|
} else {
|
|
|
|
/* detect bg for ddr4 */
|
|
|
|
coltmp = 10;
|
|
|
|
bktmp = 4;
|
|
|
|
rowtmp = 17;
|
|
|
|
|
|
|
|
col = 10;
|
|
|
|
bk = 2;
|
2019-11-15 12:04:44 +09:00
|
|
|
cap_info->col = col;
|
|
|
|
cap_info->bk = bk;
|
|
|
|
sdram_detect_bg(cap_info, coltmp);
|
2019-08-02 16:39:59 +09:00
|
|
|
}
|
2019-11-15 12:04:44 +09:00
|
|
|
|
2019-08-02 16:39:59 +09:00
|
|
|
/* detect row */
|
2019-11-15 12:04:44 +09:00
|
|
|
if (sdram_detect_row(cap_info, coltmp, bktmp, rowtmp) != 0)
|
2019-08-02 16:39:59 +09:00
|
|
|
goto cap_err;
|
|
|
|
|
2019-11-15 12:04:44 +09:00
|
|
|
/* detect row_3_4 */
|
|
|
|
sdram_detect_row_3_4(cap_info, coltmp, bktmp);
|
2019-08-02 16:39:59 +09:00
|
|
|
|
2019-11-15 12:04:44 +09:00
|
|
|
/* bw and cs detect using data training */
|
2019-08-02 16:39:59 +09:00
|
|
|
if (data_training(dram, 1, dram_type) == 0)
|
|
|
|
cs = 1;
|
|
|
|
else
|
|
|
|
cs = 0;
|
2019-11-15 12:04:44 +09:00
|
|
|
cap_info->rank = cs + 1;
|
2019-08-02 16:39:59 +09:00
|
|
|
|
|
|
|
bw = 2;
|
2019-11-15 12:04:44 +09:00
|
|
|
cap_info->bw = bw;
|
2019-08-02 16:39:59 +09:00
|
|
|
|
2019-11-15 12:04:44 +09:00
|
|
|
cap_info->cs0_high16bit_row = cap_info->cs0_row;
|
|
|
|
if (cs) {
|
|
|
|
cap_info->cs1_row = cap_info->cs0_row;
|
|
|
|
cap_info->cs1_high16bit_row = cap_info->cs0_row;
|
|
|
|
} else {
|
|
|
|
cap_info->cs1_row = 0;
|
|
|
|
cap_info->cs1_high16bit_row = 0;
|
2019-08-02 16:39:59 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
2019-11-15 12:04:44 +09:00
|
|
|
cap_err:
|
|
|
|
return -1;
|
2019-08-02 16:39:59 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static int sdram_init_detect(struct dram_info *dram,
|
|
|
|
struct rk3328_sdram_params *sdram_params)
|
|
|
|
{
|
2019-11-15 12:04:44 +09:00
|
|
|
u32 sys_reg = 0;
|
|
|
|
u32 sys_reg3 = 0;
|
|
|
|
struct sdram_cap_info *cap_info = &sdram_params->ch.cap_info;
|
|
|
|
|
2019-08-02 16:39:59 +09:00
|
|
|
debug("Starting SDRAM initialization...\n");
|
|
|
|
|
|
|
|
memcpy(&sdram_ch, &sdram_params->ch,
|
|
|
|
sizeof(struct rk3328_sdram_channel));
|
|
|
|
|
2020-01-07 16:15:20 +09:00
|
|
|
sdram_init(dram, sdram_params, 0);
|
2019-08-02 16:39:59 +09:00
|
|
|
dram_detect_cap(dram, sdram_params, 0);
|
|
|
|
|
|
|
|
/* modify bw, cs related timing */
|
2019-11-15 12:04:44 +09:00
|
|
|
pctl_remodify_sdram_params(&sdram_params->pctl_regs, cap_info,
|
|
|
|
sdram_params->base.dramtype);
|
|
|
|
|
|
|
|
if (cap_info->bw == 2)
|
|
|
|
sdram_ch.noc_timings.ddrtiming.b.bwratio = 0;
|
|
|
|
else
|
|
|
|
sdram_ch.noc_timings.ddrtiming.b.bwratio = 1;
|
|
|
|
|
2019-08-02 16:39:59 +09:00
|
|
|
/* reinit sdram by real dram cap */
|
2020-01-07 16:15:20 +09:00
|
|
|
sdram_init(dram, sdram_params, 1);
|
2019-08-02 16:39:59 +09:00
|
|
|
|
|
|
|
/* redetect cs1 row */
|
2019-11-15 12:04:44 +09:00
|
|
|
sdram_detect_cs1_row(cap_info, sdram_params->base.dramtype);
|
|
|
|
if (cap_info->cs1_row) {
|
|
|
|
sys_reg = readl(&dram->grf->os_reg[2]);
|
|
|
|
sys_reg3 = readl(&dram->grf->os_reg[3]);
|
|
|
|
SYS_REG_ENC_CS1_ROW(cap_info->cs1_row,
|
|
|
|
sys_reg, sys_reg3, 0);
|
|
|
|
writel(sys_reg, &dram->grf->os_reg[2]);
|
|
|
|
writel(sys_reg3, &dram->grf->os_reg[3]);
|
|
|
|
}
|
|
|
|
|
|
|
|
sdram_print_ddr_info(&sdram_params->ch.cap_info, &sdram_params->base);
|
2019-08-02 16:39:59 +09:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rk3328_dmc_init(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct dram_info *priv = dev_get_priv(dev);
|
|
|
|
struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
|
|
struct rk3328_sdram_params *params = &plat->sdram_params;
|
|
|
|
#else
|
|
|
|
struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
|
|
|
|
struct rk3328_sdram_params *params =
|
|
|
|
(void *)dtplat->rockchip_sdram_params;
|
|
|
|
|
|
|
|
ret = conv_of_platdata(dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
#endif
|
|
|
|
priv->phy = regmap_get_range(plat->map, 0);
|
|
|
|
priv->pctl = regmap_get_range(plat->map, 1);
|
|
|
|
priv->grf = regmap_get_range(plat->map, 2);
|
|
|
|
priv->cru = regmap_get_range(plat->map, 3);
|
|
|
|
priv->msch = regmap_get_range(plat->map, 4);
|
|
|
|
priv->ddr_grf = regmap_get_range(plat->map, 5);
|
|
|
|
|
|
|
|
debug("%s phy %p pctrl %p grf %p cru %p msch %p ddr_grf %p\n",
|
|
|
|
__func__, priv->phy, priv->pctl, priv->grf, priv->cru,
|
|
|
|
priv->msch, priv->ddr_grf);
|
|
|
|
ret = sdram_init_detect(priv, params);
|
|
|
|
if (ret < 0) {
|
|
|
|
printf("%s DRAM init failed%d\n", __func__, ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rk3328_dmc_ofdata_to_platdata(struct udevice *dev)
|
|
|
|
{
|
|
|
|
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
|
|
struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = dev_read_u32_array(dev, "rockchip,sdram-params",
|
|
|
|
(u32 *)&plat->sdram_params,
|
|
|
|
sizeof(plat->sdram_params) / sizeof(u32));
|
|
|
|
if (ret) {
|
|
|
|
printf("%s: Cannot read rockchip,sdram-params %d\n",
|
|
|
|
__func__, ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
ret = regmap_init_mem(dev, &plat->map);
|
|
|
|
if (ret)
|
|
|
|
printf("%s: regmap failed %d\n", __func__, ret);
|
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
2017-06-23 17:11:07 +09:00
|
|
|
static int rk3328_dmc_probe(struct udevice *dev)
|
|
|
|
{
|
2019-08-02 16:39:59 +09:00
|
|
|
#ifdef CONFIG_TPL_BUILD
|
|
|
|
if (rk3328_dmc_init(dev))
|
|
|
|
return 0;
|
|
|
|
#else
|
2017-06-23 17:11:07 +09:00
|
|
|
struct dram_info *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
|
|
|
debug("%s: grf=%p\n", __func__, priv->grf);
|
|
|
|
priv->info.base = CONFIG_SYS_SDRAM_BASE;
|
|
|
|
priv->info.size = rockchip_sdram_size(
|
|
|
|
(phys_addr_t)&priv->grf->os_reg[2]);
|
2019-08-02 16:39:59 +09:00
|
|
|
#endif
|
2017-06-23 17:11:07 +09:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rk3328_dmc_get_info(struct udevice *dev, struct ram_info *info)
|
|
|
|
{
|
|
|
|
struct dram_info *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
*info = priv->info;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct ram_ops rk3328_dmc_ops = {
|
|
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.get_info = rk3328_dmc_get_info,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct udevice_id rk3328_dmc_ids[] = {
|
|
|
|
{ .compatible = "rockchip,rk3328-dmc" },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(dmc_rk3328) = {
|
|
|
|
.name = "rockchip_rk3328_dmc",
|
|
|
|
.id = UCLASS_RAM,
|
|
|
|
.of_match = rk3328_dmc_ids,
|
|
|
|
.ops = &rk3328_dmc_ops,
|
2019-08-02 16:39:59 +09:00
|
|
|
#ifdef CONFIG_TPL_BUILD
|
|
|
|
.ofdata_to_platdata = rk3328_dmc_ofdata_to_platdata,
|
|
|
|
#endif
|
2017-06-23 17:11:07 +09:00
|
|
|
.probe = rk3328_dmc_probe,
|
|
|
|
.priv_auto_alloc_size = sizeof(struct dram_info),
|
2019-08-02 16:39:59 +09:00
|
|
|
#ifdef CONFIG_TPL_BUILD
|
|
|
|
.platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
|
|
|
|
#endif
|
2017-06-23 17:11:07 +09:00
|
|
|
};
|