2018-12-20 12:33:42 +09:00
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// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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2017-06-23 17:11:07 +09:00
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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2019-08-02 16:39:59 +09:00
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#include <clk.h>
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#include <debug_uart.h>
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2017-06-23 17:11:07 +09:00
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#include <dm.h>
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2019-08-02 16:39:59 +09:00
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#include <dt-structs.h>
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2017-06-23 17:11:07 +09:00
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#include <ram.h>
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2019-08-02 16:39:59 +09:00
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#include <regmap.h>
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2017-06-23 17:11:07 +09:00
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#include <syscon.h>
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2019-08-02 16:39:59 +09:00
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#include <asm/io.h>
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2019-03-28 12:01:23 +09:00
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#include <asm/arch-rockchip/clock.h>
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2019-08-02 16:39:59 +09:00
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#include <asm/arch-rockchip/cru_rk3328.h>
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2019-03-28 12:01:23 +09:00
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#include <asm/arch-rockchip/grf_rk3328.h>
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2019-11-15 12:04:33 +09:00
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#include <asm/arch-rockchip/sdram.h>
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2019-08-02 16:39:59 +09:00
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#include <asm/arch-rockchip/sdram_rk3328.h>
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#include <asm/arch-rockchip/uart.h>
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2017-06-23 17:11:07 +09:00
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struct dram_info {
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2019-08-02 16:39:59 +09:00
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#ifdef CONFIG_TPL_BUILD
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struct rk3328_ddr_pctl_regs *pctl;
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struct rk3328_ddr_phy_regs *phy;
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struct clk ddr_clk;
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struct rk3328_cru *cru;
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struct rk3328_msch_regs *msch;
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struct rk3328_ddr_grf_regs *ddr_grf;
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#endif
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2017-06-23 17:11:07 +09:00
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struct ram_info info;
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struct rk3328_grf_regs *grf;
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};
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2019-08-02 16:39:59 +09:00
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#ifdef CONFIG_TPL_BUILD
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struct rk3328_sdram_channel sdram_ch;
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struct rockchip_dmc_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_rockchip_rk3328_dmc dtplat;
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#else
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struct rk3328_sdram_params sdram_params;
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#endif
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struct regmap *map;
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};
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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static int conv_of_platdata(struct udevice *dev)
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{
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struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
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struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
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int ret;
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ret = regmap_init_mem_platdata(dev, dtplat->reg,
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ARRAY_SIZE(dtplat->reg) / 2,
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&plat->map);
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if (ret)
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return ret;
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return 0;
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}
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#endif
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static void rkclk_ddr_reset(struct dram_info *dram,
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u32 ctl_srstn, u32 ctl_psrstn,
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u32 phy_srstn, u32 phy_psrstn)
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{
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writel(ddrctrl_srstn_req(ctl_srstn) | ddrctrl_psrstn_req(ctl_psrstn) |
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ddrphy_srstn_req(phy_srstn) | ddrphy_psrstn_req(phy_psrstn),
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&dram->cru->softrst_con[5]);
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writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]);
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}
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static void rkclk_set_dpll(struct dram_info *dram, unsigned int mhz)
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{
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unsigned int refdiv, postdiv1, postdiv2, fbdiv;
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int delay = 1000;
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refdiv = 1;
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if (mhz <= 300) {
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postdiv1 = 4;
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postdiv2 = 2;
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} else if (mhz <= 400) {
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postdiv1 = 6;
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postdiv2 = 1;
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} else if (mhz <= 600) {
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postdiv1 = 4;
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postdiv2 = 1;
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} else if (mhz <= 800) {
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postdiv1 = 3;
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postdiv2 = 1;
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} else if (mhz <= 1600) {
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postdiv1 = 2;
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postdiv2 = 1;
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} else {
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postdiv1 = 1;
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postdiv2 = 1;
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}
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fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24;
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writel(((0x1 << 4) << 16) | (0 << 4), &dram->cru->mode_con);
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writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]);
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writel(DSMPD(1) | POSTDIV2(postdiv2) | REFDIV(refdiv),
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&dram->cru->dpll_con[1]);
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while (delay > 0) {
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udelay(1);
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if (LOCK(readl(&dram->cru->dpll_con[1])))
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break;
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delay--;
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}
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writel(((0x1 << 4) << 16) | (1 << 4), &dram->cru->mode_con);
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}
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static void rkclk_configure_ddr(struct dram_info *dram,
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struct rk3328_sdram_params *sdram_params)
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{
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void __iomem *phy_base = dram->phy;
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/* choose DPLL for ddr clk source */
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clrbits_le32(PHY_REG(phy_base, 0xef), 1 << 7);
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/* for inno ddr phy need 2*freq */
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rkclk_set_dpll(dram, sdram_params->ddr_freq * 2);
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}
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static void phy_soft_reset(struct dram_info *dram)
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{
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void __iomem *phy_base = dram->phy;
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clrbits_le32(PHY_REG(phy_base, 0), 0x3 << 2);
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udelay(1);
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setbits_le32(PHY_REG(phy_base, 0), ANALOG_DERESET);
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udelay(5);
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setbits_le32(PHY_REG(phy_base, 0), DIGITAL_DERESET);
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udelay(1);
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}
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static int pctl_cfg(struct dram_info *dram,
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struct rk3328_sdram_params *sdram_params)
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{
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u32 i;
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void __iomem *pctl_base = dram->pctl;
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for (i = 0; sdram_params->pctl_regs.pctl[i][0] != 0xFFFFFFFF; i++) {
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writel(sdram_params->pctl_regs.pctl[i][1],
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pctl_base + sdram_params->pctl_regs.pctl[i][0]);
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}
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clrsetbits_le32(pctl_base + DDR_PCTL2_PWRTMG,
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(0xff << 16) | 0x1f,
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((SR_IDLE & 0xff) << 16) | (PD_IDLE & 0x1f));
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/*
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* dfi_lp_en_pd=1,dfi_lp_wakeup_pd=2
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* hw_lp_idle_x32=1
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*/
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if (sdram_params->dramtype == LPDDR3) {
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setbits_le32(pctl_base + DDR_PCTL2_DFILPCFG0, 1);
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clrsetbits_le32(pctl_base + DDR_PCTL2_DFILPCFG0,
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0xf << 4,
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2 << 4);
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}
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clrsetbits_le32(pctl_base + DDR_PCTL2_HWLPCTL,
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0xfff << 16,
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1 << 16);
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/* disable zqcs */
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setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1u << 31);
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setbits_le32(pctl_base + 0x2000 + DDR_PCTL2_ZQCTL0, 1u << 31);
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return 0;
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}
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/* return ddrconfig value
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* (-1), find ddrconfig fail
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* other, the ddrconfig value
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* only support cs0_row >= cs1_row
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*/
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static unsigned int calculate_ddrconfig(struct rk3328_sdram_params *sdram_params)
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{
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static const u16 ddr_cfg_2_rbc[] = {
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/***************************
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* [5:4] row(13+n)
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* [3] cs(0:0 cs, 1:2 cs)
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* [2] bank(0:0bank,1:8bank)
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* [1:0] col(11+n)
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****************************/
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/* row, cs, bank, col */
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((3 << 4) | (0 << 3) | (1 << 2) | 0),
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((3 << 4) | (0 << 3) | (1 << 2) | 1),
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((2 << 4) | (0 << 3) | (1 << 2) | 2),
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((3 << 4) | (0 << 3) | (1 << 2) | 2),
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((2 << 4) | (0 << 3) | (1 << 2) | 3),
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((3 << 4) | (1 << 3) | (1 << 2) | 0),
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((3 << 4) | (1 << 3) | (1 << 2) | 1),
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((2 << 4) | (1 << 3) | (1 << 2) | 2),
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((3 << 4) | (0 << 3) | (0 << 2) | 1),
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((2 << 4) | (0 << 3) | (1 << 2) | 1),
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};
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static const u16 ddr4_cfg_2_rbc[] = {
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/***************************
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* [6] cs 0:0cs 1:2 cs
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* [5:3] row(13+n)
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* [2] cs(0:0 cs, 1:2 cs)
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* [1] bw 0: 16bit 1:32bit
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* [0] diebw 0:8bit 1:16bit
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***************************/
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/* cs, row, cs, bw, diebw */
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((0 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 0),
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((1 << 6) | (2 << 3) | (0 << 2) | (1 << 1) | 0),
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((0 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 0),
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((1 << 6) | (3 << 3) | (0 << 2) | (0 << 1) | 0),
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((0 << 6) | (4 << 3) | (0 << 2) | (1 << 1) | 1),
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((1 << 6) | (3 << 3) | (0 << 2) | (1 << 1) | 1),
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((1 << 6) | (4 << 3) | (0 << 2) | (0 << 1) | 1),
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((0 << 6) | (2 << 3) | (1 << 2) | (1 << 1) | 0),
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((0 << 6) | (3 << 3) | (1 << 2) | (0 << 1) | 0),
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((0 << 6) | (3 << 3) | (1 << 2) | (1 << 1) | 1),
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((0 << 6) | (4 << 3) | (1 << 2) | (0 << 1) | 1),
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};
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u32 cs, bw, die_bw, col, row, bank;
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u32 i, tmp;
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u32 ddrconf = -1;
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cs = sdram_ch.rank;
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bw = sdram_ch.bw;
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die_bw = sdram_ch.dbw;
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col = sdram_ch.col;
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row = sdram_ch.cs0_row;
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bank = sdram_ch.bk;
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if (sdram_params->dramtype == DDR4) {
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tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw;
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for (i = 10; i < 17; i++) {
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if (((tmp & 0x7) == (ddr4_cfg_2_rbc[i - 10] & 0x7)) &&
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((tmp & 0x3c) <= (ddr4_cfg_2_rbc[i - 10] & 0x3c)) &&
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((tmp & 0x40) <= (ddr4_cfg_2_rbc[i - 10] & 0x40))) {
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ddrconf = i;
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goto out;
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}
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}
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} else {
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if (bank == 2) {
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ddrconf = 8;
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goto out;
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}
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tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0);
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for (i = 0; i < 5; i++)
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if (((tmp & 0xf) == (ddr_cfg_2_rbc[i] & 0xf)) &&
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((tmp & 0x30) <= (ddr_cfg_2_rbc[i] & 0x30))) {
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ddrconf = i;
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goto out;
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}
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}
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out:
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if (ddrconf > 20)
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printf("calculate_ddrconfig error\n");
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return ddrconf;
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}
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/* n: Unit bytes */
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static void copy_to_reg(u32 *dest, u32 *src, u32 n)
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{
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int i;
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for (i = 0; i < n / sizeof(u32); i++) {
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writel(*src, dest);
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src++;
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dest++;
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}
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}
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/*******
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* calculate controller dram address map, and setting to register.
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* argument sdram_ch.ddrconf must be right value before
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* call this function.
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*******/
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static void set_ctl_address_map(struct dram_info *dram,
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struct rk3328_sdram_params *sdram_params)
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{
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void __iomem *pctl_base = dram->pctl;
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copy_to_reg((u32 *)(pctl_base + DDR_PCTL2_ADDRMAP0),
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&addrmap[sdram_ch.ddrconfig][0], 9 * 4);
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if (sdram_params->dramtype == LPDDR3 && sdram_ch.row_3_4)
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setbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6, 1 << 31);
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if (sdram_params->dramtype == DDR4 && sdram_ch.bw == 0x1)
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setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8);
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if (sdram_ch.rank == 1)
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clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP0, 0x1f, 0x1f);
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}
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static void phy_dll_bypass_set(struct dram_info *dram, u32 freq)
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{
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u32 tmp;
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void __iomem *phy_base = dram->phy;
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setbits_le32(PHY_REG(phy_base, 0x13), 1 << 4);
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clrbits_le32(PHY_REG(phy_base, 0x14), 1 << 3);
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setbits_le32(PHY_REG(phy_base, 0x26), 1 << 4);
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clrbits_le32(PHY_REG(phy_base, 0x27), 1 << 3);
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setbits_le32(PHY_REG(phy_base, 0x36), 1 << 4);
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clrbits_le32(PHY_REG(phy_base, 0x37), 1 << 3);
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setbits_le32(PHY_REG(phy_base, 0x46), 1 << 4);
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clrbits_le32(PHY_REG(phy_base, 0x47), 1 << 3);
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setbits_le32(PHY_REG(phy_base, 0x56), 1 << 4);
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clrbits_le32(PHY_REG(phy_base, 0x57), 1 << 3);
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2019-10-07 01:28:13 +09:00
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if (freq <= 400)
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2019-08-02 16:39:59 +09:00
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/* DLL bypass */
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setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);
|
|
|
|
else
|
|
|
|
clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f);
|
2019-10-07 01:28:13 +09:00
|
|
|
if (freq <= 680)
|
2019-08-02 16:39:59 +09:00
|
|
|
tmp = 2;
|
|
|
|
else
|
|
|
|
tmp = 1;
|
|
|
|
writel(tmp, PHY_REG(phy_base, 0x28));
|
|
|
|
writel(tmp, PHY_REG(phy_base, 0x38));
|
|
|
|
writel(tmp, PHY_REG(phy_base, 0x48));
|
|
|
|
writel(tmp, PHY_REG(phy_base, 0x58));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void set_ds_odt(struct dram_info *dram,
|
|
|
|
struct rk3328_sdram_params *sdram_params)
|
|
|
|
{
|
|
|
|
u32 cmd_drv, clk_drv, dqs_drv, dqs_odt;
|
|
|
|
void __iomem *phy_base = dram->phy;
|
|
|
|
|
|
|
|
if (sdram_params->dramtype == DDR3) {
|
|
|
|
cmd_drv = PHY_DDR3_RON_RTT_34ohm;
|
|
|
|
clk_drv = PHY_DDR3_RON_RTT_45ohm;
|
|
|
|
dqs_drv = PHY_DDR3_RON_RTT_34ohm;
|
|
|
|
dqs_odt = PHY_DDR3_RON_RTT_225ohm;
|
|
|
|
} else {
|
|
|
|
cmd_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm;
|
|
|
|
clk_drv = PHY_DDR4_LPDDR3_RON_RTT_43ohm;
|
|
|
|
dqs_drv = PHY_DDR4_LPDDR3_RON_RTT_34ohm;
|
|
|
|
dqs_odt = PHY_DDR4_LPDDR3_RON_RTT_240ohm;
|
|
|
|
}
|
|
|
|
/* DS */
|
|
|
|
writel(cmd_drv, PHY_REG(phy_base, 0x11));
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 0x12), 0x1f << 3, cmd_drv << 3);
|
|
|
|
writel(clk_drv, PHY_REG(phy_base, 0x16));
|
|
|
|
writel(clk_drv, PHY_REG(phy_base, 0x18));
|
|
|
|
writel(dqs_drv, PHY_REG(phy_base, 0x20));
|
|
|
|
writel(dqs_drv, PHY_REG(phy_base, 0x2f));
|
|
|
|
writel(dqs_drv, PHY_REG(phy_base, 0x30));
|
|
|
|
writel(dqs_drv, PHY_REG(phy_base, 0x3f));
|
|
|
|
writel(dqs_drv, PHY_REG(phy_base, 0x40));
|
|
|
|
writel(dqs_drv, PHY_REG(phy_base, 0x4f));
|
|
|
|
writel(dqs_drv, PHY_REG(phy_base, 0x50));
|
|
|
|
writel(dqs_drv, PHY_REG(phy_base, 0x5f));
|
|
|
|
/* ODT */
|
|
|
|
writel(dqs_odt, PHY_REG(phy_base, 0x21));
|
|
|
|
writel(dqs_odt, PHY_REG(phy_base, 0x2e));
|
|
|
|
writel(dqs_odt, PHY_REG(phy_base, 0x31));
|
|
|
|
writel(dqs_odt, PHY_REG(phy_base, 0x3e));
|
|
|
|
writel(dqs_odt, PHY_REG(phy_base, 0x41));
|
|
|
|
writel(dqs_odt, PHY_REG(phy_base, 0x4e));
|
|
|
|
writel(dqs_odt, PHY_REG(phy_base, 0x51));
|
|
|
|
writel(dqs_odt, PHY_REG(phy_base, 0x5e));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void phy_cfg(struct dram_info *dram,
|
|
|
|
struct rk3328_sdram_params *sdram_params)
|
|
|
|
{
|
|
|
|
u32 i;
|
|
|
|
void __iomem *phy_base = dram->phy;
|
|
|
|
|
|
|
|
phy_dll_bypass_set(dram, sdram_params->ddr_freq);
|
|
|
|
for (i = 0; sdram_params->phy_regs.phy[i][0] != 0xFFFFFFFF; i++) {
|
|
|
|
writel(sdram_params->phy_regs.phy[i][1],
|
|
|
|
phy_base + sdram_params->phy_regs.phy[i][0]);
|
|
|
|
}
|
|
|
|
if (sdram_ch.bw == 2) {
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 0xf << 4);
|
|
|
|
} else {
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 0), 0xf << 4, 3 << 4);
|
|
|
|
/* disable DQS2,DQS3 tx dll for saving power */
|
|
|
|
clrbits_le32(PHY_REG(phy_base, 0x46), 1 << 3);
|
|
|
|
clrbits_le32(PHY_REG(phy_base, 0x56), 1 << 3);
|
|
|
|
}
|
|
|
|
set_ds_odt(dram, sdram_params);
|
|
|
|
/* deskew */
|
|
|
|
setbits_le32(PHY_REG(phy_base, 2), 8);
|
|
|
|
copy_to_reg(PHY_REG(phy_base, 0xb0),
|
|
|
|
&sdram_params->skew.a0_a1_skew[0], 15 * 4);
|
|
|
|
copy_to_reg(PHY_REG(phy_base, 0x70),
|
|
|
|
&sdram_params->skew.cs0_dm0_skew[0], 44 * 4);
|
|
|
|
copy_to_reg(PHY_REG(phy_base, 0xc0),
|
2019-10-07 01:28:14 +09:00
|
|
|
&sdram_params->skew.cs1_dm0_skew[0], 44 * 4);
|
2019-08-02 16:39:59 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static int update_refresh_reg(struct dram_info *dram)
|
|
|
|
{
|
|
|
|
void __iomem *pctl_base = dram->pctl;
|
|
|
|
u32 ret;
|
|
|
|
|
|
|
|
ret = readl(pctl_base + DDR_PCTL2_RFSHCTL3) ^ (1 << 1);
|
|
|
|
writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int data_training(struct dram_info *dram, u32 cs, u32 dramtype)
|
|
|
|
{
|
|
|
|
u32 ret;
|
|
|
|
u32 dis_auto_zq = 0;
|
|
|
|
void __iomem *pctl_base = dram->pctl;
|
|
|
|
void __iomem *phy_base = dram->phy;
|
|
|
|
|
|
|
|
/* disable zqcs */
|
|
|
|
if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &
|
|
|
|
(1ul << 31))) {
|
|
|
|
dis_auto_zq = 1;
|
|
|
|
setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
|
|
|
|
}
|
|
|
|
/* disable auto refresh */
|
|
|
|
setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
|
|
|
|
update_refresh_reg(dram);
|
|
|
|
|
|
|
|
if (dramtype == DDR4) {
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0);
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0);
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0);
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0);
|
|
|
|
}
|
|
|
|
/* choose training cs */
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs));
|
|
|
|
/* enable gate training */
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 1);
|
|
|
|
udelay(50);
|
|
|
|
ret = readl(PHY_REG(phy_base, 0xff));
|
|
|
|
/* disable gate training */
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 2), 0x33, (0x20 >> cs) | 0);
|
|
|
|
/* restore zqcs */
|
|
|
|
if (dis_auto_zq)
|
|
|
|
clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
|
|
|
|
/* restore auto refresh */
|
|
|
|
clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
|
|
|
|
update_refresh_reg(dram);
|
|
|
|
|
|
|
|
if (dramtype == DDR4) {
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 0x29), 0x3, 0x2);
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 0x39), 0x3, 0x2);
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 0x49), 0x3, 0x2);
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 0x59), 0x3, 0x2);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ret & 0x10) {
|
|
|
|
ret = -1;
|
|
|
|
} else {
|
|
|
|
ret = (ret & 0xf) ^ (readl(PHY_REG(phy_base, 0)) >> 4);
|
|
|
|
ret = (ret == 0) ? 0 : -1;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* rank = 1: cs0
|
|
|
|
* rank = 2: cs1
|
|
|
|
* rank = 3: cs0 & cs1
|
|
|
|
* note: be careful of keep mr original val
|
|
|
|
*/
|
|
|
|
static int write_mr(struct dram_info *dram, u32 rank, u32 mr_num, u32 arg,
|
|
|
|
u32 dramtype)
|
|
|
|
{
|
|
|
|
void __iomem *pctl_base = dram->pctl;
|
|
|
|
|
|
|
|
while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
|
|
|
|
continue;
|
|
|
|
if (dramtype == DDR3 || dramtype == DDR4) {
|
|
|
|
writel((mr_num << 12) | (rank << 4) | (0 << 0),
|
|
|
|
pctl_base + DDR_PCTL2_MRCTRL0);
|
|
|
|
writel(arg, pctl_base + DDR_PCTL2_MRCTRL1);
|
|
|
|
} else {
|
|
|
|
writel((rank << 4) | (0 << 0),
|
|
|
|
pctl_base + DDR_PCTL2_MRCTRL0);
|
|
|
|
writel((mr_num << 8) | (arg & 0xff),
|
|
|
|
pctl_base + DDR_PCTL2_MRCTRL1);
|
|
|
|
}
|
|
|
|
|
|
|
|
setbits_le32(pctl_base + DDR_PCTL2_MRCTRL0, 1u << 31);
|
|
|
|
while (readl(pctl_base + DDR_PCTL2_MRCTRL0) & (1u << 31))
|
|
|
|
continue;
|
|
|
|
while (readl(pctl_base + DDR_PCTL2_MRSTAT) & MR_WR_BUSY)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* rank : 1:cs0, 2:cs1, 3:cs0&cs1
|
|
|
|
* vrefrate: 4500: 45%,
|
|
|
|
*/
|
|
|
|
static int write_vrefdq(struct dram_info *dram, u32 rank, u32 vrefrate,
|
|
|
|
u32 dramtype)
|
|
|
|
{
|
|
|
|
u32 tccd_l, value;
|
|
|
|
u32 dis_auto_zq = 0;
|
|
|
|
void __iomem *pctl_base = dram->pctl;
|
|
|
|
|
|
|
|
if (dramtype != DDR4 || vrefrate < 4500 || vrefrate > 9200)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
tccd_l = (readl(pctl_base + DDR_PCTL2_DRAMTMG4) >> 16) & 0xf;
|
|
|
|
tccd_l = (tccd_l - 4) << 10;
|
|
|
|
|
|
|
|
if (vrefrate > 7500) {
|
|
|
|
/* range 1 */
|
|
|
|
value = ((vrefrate - 6000) / 65) | tccd_l;
|
|
|
|
} else {
|
|
|
|
/* range 2 */
|
|
|
|
value = ((vrefrate - 4500) / 65) | tccd_l | (1 << 6);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* disable zqcs */
|
|
|
|
if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) &
|
|
|
|
(1ul << 31))) {
|
|
|
|
dis_auto_zq = 1;
|
|
|
|
setbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
|
|
|
|
}
|
|
|
|
/* disable auto refresh */
|
|
|
|
setbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
|
|
|
|
update_refresh_reg(dram);
|
|
|
|
|
|
|
|
/* enable vrefdq calibratin */
|
|
|
|
write_mr(dram, rank, 6, value | (1 << 7), dramtype);
|
|
|
|
udelay(1);/* tvrefdqe */
|
|
|
|
/* write vrefdq value */
|
|
|
|
write_mr(dram, rank, 6, value | (1 << 7), dramtype);
|
|
|
|
udelay(1);/* tvref_time */
|
|
|
|
write_mr(dram, rank, 6, value | (0 << 7), dramtype);
|
|
|
|
udelay(1);/* tvrefdqx */
|
|
|
|
|
|
|
|
/* restore zqcs */
|
|
|
|
if (dis_auto_zq)
|
|
|
|
clrbits_le32(pctl_base + DDR_PCTL2_ZQCTL0, 1 << 31);
|
|
|
|
/* restore auto refresh */
|
|
|
|
clrbits_le32(pctl_base + DDR_PCTL2_RFSHCTL3, 1);
|
|
|
|
update_refresh_reg(dram);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#define _MAX_(x, y) ((x) > (y) ? (x) : (y))
|
|
|
|
|
|
|
|
static void rx_deskew_switch_adjust(struct dram_info *dram)
|
|
|
|
{
|
|
|
|
u32 i, deskew_val;
|
|
|
|
u32 gate_val = 0;
|
|
|
|
void __iomem *phy_base = dram->phy;
|
|
|
|
|
|
|
|
for (i = 0; i < 4; i++)
|
|
|
|
gate_val = _MAX_(readl(PHY_REG(phy_base, 0xfb + i)), gate_val);
|
|
|
|
|
|
|
|
deskew_val = (gate_val >> 3) + 1;
|
|
|
|
deskew_val = (deskew_val > 0x1f) ? 0x1f : deskew_val;
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0xc, (deskew_val & 0x3) << 2);
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 0x6f), 0x7 << 4,
|
|
|
|
(deskew_val & 0x1c) << 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
#undef _MAX_
|
|
|
|
|
|
|
|
static void tx_deskew_switch_adjust(struct dram_info *dram)
|
|
|
|
{
|
|
|
|
void __iomem *phy_base = dram->phy;
|
|
|
|
|
|
|
|
clrsetbits_le32(PHY_REG(phy_base, 0x6e), 0x3, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void set_ddrconfig(struct dram_info *dram, u32 ddrconfig)
|
|
|
|
{
|
|
|
|
writel(ddrconfig, &dram->msch->ddrconf);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void dram_all_config(struct dram_info *dram,
|
|
|
|
struct rk3328_sdram_params *sdram_params)
|
|
|
|
{
|
|
|
|
u32 sys_reg = 0, tmp = 0;
|
|
|
|
|
|
|
|
set_ddrconfig(dram, sdram_ch.ddrconfig);
|
|
|
|
|
|
|
|
sys_reg |= SYS_REG_ENC_DDRTYPE(sdram_params->dramtype);
|
|
|
|
sys_reg |= SYS_REG_ENC_ROW_3_4(sdram_ch.row_3_4, 0);
|
|
|
|
sys_reg |= SYS_REG_ENC_RANK(sdram_ch.rank, 0);
|
|
|
|
sys_reg |= SYS_REG_ENC_COL(sdram_ch.col, 0);
|
|
|
|
sys_reg |= SYS_REG_ENC_BK(sdram_ch.bk, 0);
|
|
|
|
SYS_REG_ENC_CS0_ROW(sdram_ch.cs0_row, sys_reg, tmp, 0);
|
|
|
|
if (sdram_ch.cs1_row)
|
|
|
|
SYS_REG_ENC_CS1_ROW(sdram_ch.cs1_row, sys_reg, tmp, 0);
|
|
|
|
sys_reg |= SYS_REG_ENC_BW(sdram_ch.bw, 0);
|
|
|
|
sys_reg |= SYS_REG_ENC_DBW(sdram_ch.dbw, 0);
|
|
|
|
|
|
|
|
writel(sys_reg, &dram->grf->os_reg[2]);
|
|
|
|
|
|
|
|
writel(sdram_ch.noc_timings.ddrtiming.d32, &dram->msch->ddrtiming);
|
|
|
|
|
|
|
|
writel(sdram_ch.noc_timings.ddrmode.d32, &dram->msch->ddrmode);
|
|
|
|
writel(sdram_ch.noc_timings.readlatency, &dram->msch->readlatency);
|
|
|
|
|
|
|
|
writel(sdram_ch.noc_timings.activate.d32, &dram->msch->activate);
|
|
|
|
writel(sdram_ch.noc_timings.devtodev.d32, &dram->msch->devtodev);
|
|
|
|
writel(sdram_ch.noc_timings.ddr4timing.d32, &dram->msch->ddr4_timing);
|
|
|
|
writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging0);
|
|
|
|
writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging1);
|
|
|
|
writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging2);
|
|
|
|
writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging3);
|
|
|
|
writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging4);
|
|
|
|
writel(sdram_ch.noc_timings.agingx0, &dram->msch->aging5);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void enable_low_power(struct dram_info *dram,
|
|
|
|
struct rk3328_sdram_params *sdram_params)
|
|
|
|
{
|
|
|
|
void __iomem *pctl_base = dram->pctl;
|
|
|
|
|
|
|
|
/* enable upctl2 axi clock auto gating */
|
|
|
|
writel(0x00800000, &dram->ddr_grf->ddr_grf_con[0]);
|
|
|
|
writel(0x20012001, &dram->ddr_grf->ddr_grf_con[2]);
|
|
|
|
/* enable upctl2 core clock auto gating */
|
|
|
|
writel(0x001e001a, &dram->ddr_grf->ddr_grf_con[2]);
|
|
|
|
/* enable sr, pd */
|
|
|
|
if (PD_IDLE == 0)
|
|
|
|
clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
|
|
|
|
else
|
|
|
|
setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 1));
|
|
|
|
if (SR_IDLE == 0)
|
|
|
|
clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
|
|
|
|
else
|
|
|
|
setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1);
|
|
|
|
setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3));
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sdram_init(struct dram_info *dram,
|
|
|
|
struct rk3328_sdram_params *sdram_params, u32 pre_init)
|
|
|
|
{
|
|
|
|
void __iomem *pctl_base = dram->pctl;
|
|
|
|
|
|
|
|
rkclk_ddr_reset(dram, 1, 1, 1, 1);
|
|
|
|
udelay(10);
|
|
|
|
/*
|
|
|
|
* dereset ddr phy psrstn to config pll,
|
|
|
|
* if using phy pll psrstn must be dereset
|
|
|
|
* before config pll
|
|
|
|
*/
|
|
|
|
rkclk_ddr_reset(dram, 1, 1, 1, 0);
|
|
|
|
rkclk_configure_ddr(dram, sdram_params);
|
|
|
|
if (pre_init == 0) {
|
|
|
|
switch (sdram_params->dramtype) {
|
|
|
|
case DDR3:
|
|
|
|
printf("DDR3\n");
|
|
|
|
break;
|
|
|
|
case DDR4:
|
|
|
|
printf("DDR4\n");
|
|
|
|
break;
|
|
|
|
case LPDDR3:
|
|
|
|
default:
|
|
|
|
printf("LPDDR3\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* release phy srst to provide clk to ctrl */
|
|
|
|
rkclk_ddr_reset(dram, 1, 1, 0, 0);
|
|
|
|
udelay(10);
|
|
|
|
phy_soft_reset(dram);
|
|
|
|
/* release ctrl presetn, and config ctl registers */
|
|
|
|
rkclk_ddr_reset(dram, 1, 0, 0, 0);
|
|
|
|
pctl_cfg(dram, sdram_params);
|
|
|
|
sdram_ch.ddrconfig = calculate_ddrconfig(sdram_params);
|
|
|
|
set_ctl_address_map(dram, sdram_params);
|
|
|
|
phy_cfg(dram, sdram_params);
|
|
|
|
|
|
|
|
/* enable dfi_init_start to init phy after ctl srstn deassert */
|
|
|
|
setbits_le32(pctl_base + DDR_PCTL2_DFIMISC, (1 << 5) | (1 << 4));
|
|
|
|
rkclk_ddr_reset(dram, 0, 0, 0, 0);
|
|
|
|
/* wait for dfi_init_done and dram init complete */
|
|
|
|
while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* do ddr gate training */
|
|
|
|
if (data_training(dram, 0, sdram_params->dramtype) != 0) {
|
|
|
|
printf("data training error\n");
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sdram_params->dramtype == DDR4)
|
|
|
|
write_vrefdq(dram, 0x3, 5670, sdram_params->dramtype);
|
|
|
|
|
|
|
|
if (pre_init == 0) {
|
|
|
|
rx_deskew_switch_adjust(dram);
|
|
|
|
tx_deskew_switch_adjust(dram);
|
|
|
|
}
|
|
|
|
|
|
|
|
dram_all_config(dram, sdram_params);
|
|
|
|
enable_low_power(dram, sdram_params);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u64 dram_detect_cap(struct dram_info *dram,
|
|
|
|
struct rk3328_sdram_params *sdram_params,
|
|
|
|
unsigned char channel)
|
|
|
|
{
|
|
|
|
void __iomem *pctl_base = dram->pctl;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* for ddr3: ddrconf = 3
|
|
|
|
* for ddr4: ddrconf = 12
|
|
|
|
* for lpddr3: ddrconf = 3
|
|
|
|
* default bw = 1
|
|
|
|
*/
|
|
|
|
u32 bk, bktmp;
|
|
|
|
u32 col, coltmp;
|
|
|
|
u32 row, rowtmp, row_3_4;
|
|
|
|
void __iomem *test_addr, *test_addr1;
|
|
|
|
u32 dbw;
|
|
|
|
u32 cs;
|
|
|
|
u32 bw = 1;
|
|
|
|
u64 cap = 0;
|
|
|
|
u32 dram_type = sdram_params->dramtype;
|
|
|
|
u32 pwrctl;
|
|
|
|
|
|
|
|
if (dram_type != DDR4) {
|
|
|
|
/* detect col and bk for ddr3/lpddr3 */
|
|
|
|
coltmp = 12;
|
|
|
|
bktmp = 3;
|
|
|
|
rowtmp = 16;
|
|
|
|
|
|
|
|
for (col = coltmp; col >= 9; col -= 1) {
|
|
|
|
writel(0, SDRAM_ADDR);
|
|
|
|
test_addr = (void __iomem *)(SDRAM_ADDR +
|
|
|
|
(1ul << (col + bw - 1ul)));
|
|
|
|
writel(PATTERN, test_addr);
|
|
|
|
if ((readl(test_addr) == PATTERN) &&
|
|
|
|
(readl(SDRAM_ADDR) == 0))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (col == 8) {
|
|
|
|
printf("col error\n");
|
|
|
|
goto cap_err;
|
|
|
|
}
|
|
|
|
|
|
|
|
test_addr = (void __iomem *)(SDRAM_ADDR +
|
|
|
|
(1ul << (coltmp + bktmp + bw - 1ul)));
|
|
|
|
writel(0, SDRAM_ADDR);
|
|
|
|
writel(PATTERN, test_addr);
|
|
|
|
if ((readl(test_addr) == PATTERN) &&
|
|
|
|
(readl(SDRAM_ADDR) == 0))
|
|
|
|
bk = 3;
|
|
|
|
else
|
|
|
|
bk = 2;
|
|
|
|
if (dram_type == LPDDR3)
|
|
|
|
dbw = 2;
|
|
|
|
else
|
|
|
|
dbw = 1;
|
|
|
|
} else {
|
|
|
|
/* detect bg for ddr4 */
|
|
|
|
coltmp = 10;
|
|
|
|
bktmp = 4;
|
|
|
|
rowtmp = 17;
|
|
|
|
|
|
|
|
col = 10;
|
|
|
|
bk = 2;
|
|
|
|
test_addr = (void __iomem *)(SDRAM_ADDR +
|
|
|
|
(1ul << (coltmp + bw + 1ul)));
|
|
|
|
writel(0, SDRAM_ADDR);
|
|
|
|
writel(PATTERN, test_addr);
|
|
|
|
if ((readl(test_addr) == PATTERN) &&
|
|
|
|
(readl(SDRAM_ADDR) == 0))
|
|
|
|
dbw = 0;
|
|
|
|
else
|
|
|
|
dbw = 1;
|
|
|
|
}
|
|
|
|
/* detect row */
|
|
|
|
for (row = rowtmp; row > 12; row--) {
|
|
|
|
writel(0, SDRAM_ADDR);
|
|
|
|
test_addr = (void __iomem *)(SDRAM_ADDR +
|
|
|
|
(1ul << (row + bktmp + coltmp + bw - 1ul)));
|
|
|
|
writel(PATTERN, test_addr);
|
|
|
|
if ((readl(test_addr) == PATTERN) &&
|
|
|
|
(readl(SDRAM_ADDR) == 0))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (row == 12) {
|
|
|
|
printf("row error");
|
|
|
|
goto cap_err;
|
|
|
|
}
|
|
|
|
/* detect row_3_4 */
|
|
|
|
test_addr = SDRAM_ADDR;
|
|
|
|
test_addr1 = (void __iomem *)(SDRAM_ADDR +
|
|
|
|
(0x3ul << (row + bktmp + coltmp + bw - 1ul - 1ul)));
|
|
|
|
|
|
|
|
writel(0, test_addr);
|
|
|
|
writel(PATTERN, test_addr1);
|
|
|
|
if ((readl(test_addr) == 0) &&
|
|
|
|
(readl(test_addr1) == PATTERN))
|
|
|
|
row_3_4 = 0;
|
|
|
|
else
|
|
|
|
row_3_4 = 1;
|
|
|
|
|
|
|
|
/* disable auto low-power */
|
|
|
|
pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL);
|
|
|
|
writel(0, pctl_base + DDR_PCTL2_PWRCTL);
|
|
|
|
|
|
|
|
/* bw and cs detect using phy read gate training */
|
|
|
|
if (data_training(dram, 1, dram_type) == 0)
|
|
|
|
cs = 1;
|
|
|
|
else
|
|
|
|
cs = 0;
|
|
|
|
|
|
|
|
bw = 2;
|
|
|
|
|
|
|
|
/* restore auto low-power */
|
|
|
|
writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL);
|
|
|
|
|
|
|
|
sdram_ch.rank = cs + 1;
|
|
|
|
sdram_ch.col = col;
|
|
|
|
sdram_ch.bk = bk;
|
|
|
|
sdram_ch.dbw = dbw;
|
|
|
|
sdram_ch.bw = bw;
|
|
|
|
sdram_ch.cs0_row = row;
|
|
|
|
if (cs)
|
|
|
|
sdram_ch.cs1_row = row;
|
|
|
|
else
|
|
|
|
sdram_ch.cs1_row = 0;
|
|
|
|
sdram_ch.row_3_4 = row_3_4;
|
|
|
|
|
|
|
|
if (dram_type == DDR4)
|
|
|
|
cap = 1llu << (cs + row + bk + col + ((dbw == 0) ? 2 : 1) + bw);
|
|
|
|
else
|
|
|
|
cap = 1llu << (cs + row + bk + col + bw);
|
|
|
|
|
|
|
|
return cap;
|
|
|
|
|
|
|
|
cap_err:
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 remodify_sdram_params(struct rk3328_sdram_params *sdram_params)
|
|
|
|
{
|
|
|
|
u32 tmp = 0, tmp_adr = 0, i;
|
|
|
|
|
|
|
|
for (i = 0; sdram_params->pctl_regs.pctl[i][0] != 0xFFFFFFFF; i++) {
|
|
|
|
if (sdram_params->pctl_regs.pctl[i][0] == 0) {
|
|
|
|
tmp = sdram_params->pctl_regs.pctl[i][1];/* MSTR */
|
|
|
|
tmp_adr = i;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
tmp &= ~((3ul << 30) | (3ul << 24) | (3ul << 12));
|
|
|
|
|
|
|
|
switch (sdram_ch.dbw) {
|
|
|
|
case 2:
|
|
|
|
tmp |= (3ul << 30);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
tmp |= (2ul << 30);
|
|
|
|
break;
|
|
|
|
case 0:
|
|
|
|
default:
|
|
|
|
tmp |= (1ul << 30);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (sdram_ch.rank == 2)
|
|
|
|
tmp |= 3 << 24;
|
|
|
|
else
|
|
|
|
tmp |= 1 << 24;
|
|
|
|
|
|
|
|
tmp |= (2 - sdram_ch.bw) << 12;
|
|
|
|
|
|
|
|
sdram_params->pctl_regs.pctl[tmp_adr][1] = tmp;
|
|
|
|
|
|
|
|
if (sdram_ch.bw == 2)
|
|
|
|
sdram_ch.noc_timings.ddrtiming.b.bwratio = 0;
|
|
|
|
else
|
|
|
|
sdram_ch.noc_timings.ddrtiming.b.bwratio = 1;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int dram_detect_cs1_row(struct rk3328_sdram_params *sdram_params,
|
|
|
|
unsigned char channel)
|
|
|
|
{
|
|
|
|
u32 ret = 0;
|
|
|
|
u32 cs1_bit;
|
|
|
|
void __iomem *test_addr, *cs1_addr;
|
|
|
|
u32 row, bktmp, coltmp, bw;
|
|
|
|
u32 ddrconf = sdram_ch.ddrconfig;
|
|
|
|
|
|
|
|
if (sdram_ch.rank == 2) {
|
|
|
|
cs1_bit = addrmap[ddrconf][0] + 8;
|
|
|
|
|
|
|
|
if (cs1_bit > 31)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
cs1_addr = (void __iomem *)(1ul << cs1_bit);
|
|
|
|
if (cs1_bit < 20)
|
|
|
|
cs1_bit = 1;
|
|
|
|
else
|
|
|
|
cs1_bit = 0;
|
|
|
|
|
|
|
|
if (sdram_params->dramtype == DDR4) {
|
|
|
|
if (sdram_ch.dbw == 0)
|
|
|
|
bktmp = sdram_ch.bk + 2;
|
|
|
|
else
|
|
|
|
bktmp = sdram_ch.bk + 1;
|
|
|
|
} else {
|
|
|
|
bktmp = sdram_ch.bk;
|
|
|
|
}
|
|
|
|
bw = sdram_ch.bw;
|
|
|
|
coltmp = sdram_ch.col;
|
|
|
|
|
|
|
|
/* detect cs1 row */
|
|
|
|
for (row = sdram_ch.cs0_row; row > 12; row--) {
|
|
|
|
test_addr = (void __iomem *)(SDRAM_ADDR + cs1_addr +
|
|
|
|
(1ul << (row + cs1_bit + bktmp +
|
|
|
|
coltmp + bw - 1ul)));
|
|
|
|
writel(0, SDRAM_ADDR + cs1_addr);
|
|
|
|
writel(PATTERN, test_addr);
|
|
|
|
if ((readl(test_addr) == PATTERN) &&
|
|
|
|
(readl(SDRAM_ADDR + cs1_addr) == 0)) {
|
|
|
|
ret = row;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sdram_init_detect(struct dram_info *dram,
|
|
|
|
struct rk3328_sdram_params *sdram_params)
|
|
|
|
{
|
|
|
|
debug("Starting SDRAM initialization...\n");
|
|
|
|
|
|
|
|
memcpy(&sdram_ch, &sdram_params->ch,
|
|
|
|
sizeof(struct rk3328_sdram_channel));
|
|
|
|
|
|
|
|
sdram_init(dram, sdram_params, 1);
|
|
|
|
dram_detect_cap(dram, sdram_params, 0);
|
|
|
|
|
|
|
|
/* modify bw, cs related timing */
|
|
|
|
remodify_sdram_params(sdram_params);
|
|
|
|
/* reinit sdram by real dram cap */
|
|
|
|
sdram_init(dram, sdram_params, 0);
|
|
|
|
|
|
|
|
/* redetect cs1 row */
|
|
|
|
sdram_ch.cs1_row =
|
|
|
|
dram_detect_cs1_row(sdram_params, 0);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rk3328_dmc_init(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct dram_info *priv = dev_get_priv(dev);
|
|
|
|
struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
|
|
struct rk3328_sdram_params *params = &plat->sdram_params;
|
|
|
|
#else
|
|
|
|
struct dtd_rockchip_rk3328_dmc *dtplat = &plat->dtplat;
|
|
|
|
struct rk3328_sdram_params *params =
|
|
|
|
(void *)dtplat->rockchip_sdram_params;
|
|
|
|
|
|
|
|
ret = conv_of_platdata(dev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
#endif
|
|
|
|
priv->phy = regmap_get_range(plat->map, 0);
|
|
|
|
priv->pctl = regmap_get_range(plat->map, 1);
|
|
|
|
priv->grf = regmap_get_range(plat->map, 2);
|
|
|
|
priv->cru = regmap_get_range(plat->map, 3);
|
|
|
|
priv->msch = regmap_get_range(plat->map, 4);
|
|
|
|
priv->ddr_grf = regmap_get_range(plat->map, 5);
|
|
|
|
|
|
|
|
debug("%s phy %p pctrl %p grf %p cru %p msch %p ddr_grf %p\n",
|
|
|
|
__func__, priv->phy, priv->pctl, priv->grf, priv->cru,
|
|
|
|
priv->msch, priv->ddr_grf);
|
|
|
|
ret = sdram_init_detect(priv, params);
|
|
|
|
if (ret < 0) {
|
|
|
|
printf("%s DRAM init failed%d\n", __func__, ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rk3328_dmc_ofdata_to_platdata(struct udevice *dev)
|
|
|
|
{
|
|
|
|
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
|
|
struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = dev_read_u32_array(dev, "rockchip,sdram-params",
|
|
|
|
(u32 *)&plat->sdram_params,
|
|
|
|
sizeof(plat->sdram_params) / sizeof(u32));
|
|
|
|
if (ret) {
|
|
|
|
printf("%s: Cannot read rockchip,sdram-params %d\n",
|
|
|
|
__func__, ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
ret = regmap_init_mem(dev, &plat->map);
|
|
|
|
if (ret)
|
|
|
|
printf("%s: regmap failed %d\n", __func__, ret);
|
|
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
2017-06-23 17:11:07 +09:00
|
|
|
static int rk3328_dmc_probe(struct udevice *dev)
|
|
|
|
{
|
2019-08-02 16:39:59 +09:00
|
|
|
#ifdef CONFIG_TPL_BUILD
|
|
|
|
if (rk3328_dmc_init(dev))
|
|
|
|
return 0;
|
|
|
|
#else
|
2017-06-23 17:11:07 +09:00
|
|
|
struct dram_info *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
|
|
|
debug("%s: grf=%p\n", __func__, priv->grf);
|
|
|
|
priv->info.base = CONFIG_SYS_SDRAM_BASE;
|
|
|
|
priv->info.size = rockchip_sdram_size(
|
|
|
|
(phys_addr_t)&priv->grf->os_reg[2]);
|
2019-08-02 16:39:59 +09:00
|
|
|
#endif
|
2017-06-23 17:11:07 +09:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int rk3328_dmc_get_info(struct udevice *dev, struct ram_info *info)
|
|
|
|
{
|
|
|
|
struct dram_info *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
*info = priv->info;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct ram_ops rk3328_dmc_ops = {
|
|
|
|
.get_info = rk3328_dmc_get_info,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct udevice_id rk3328_dmc_ids[] = {
|
|
|
|
{ .compatible = "rockchip,rk3328-dmc" },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(dmc_rk3328) = {
|
|
|
|
.name = "rockchip_rk3328_dmc",
|
|
|
|
.id = UCLASS_RAM,
|
|
|
|
.of_match = rk3328_dmc_ids,
|
|
|
|
.ops = &rk3328_dmc_ops,
|
2019-08-02 16:39:59 +09:00
|
|
|
#ifdef CONFIG_TPL_BUILD
|
|
|
|
.ofdata_to_platdata = rk3328_dmc_ofdata_to_platdata,
|
|
|
|
#endif
|
2017-06-23 17:11:07 +09:00
|
|
|
.probe = rk3328_dmc_probe,
|
|
|
|
.priv_auto_alloc_size = sizeof(struct dram_info),
|
2019-08-02 16:39:59 +09:00
|
|
|
#ifdef CONFIG_TPL_BUILD
|
|
|
|
.platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
|
|
|
|
#endif
|
2017-06-23 17:11:07 +09:00
|
|
|
};
|