u-boot-brain/arch/riscv/cpu/ax25/Kconfig

config RISCV_NDS
	bool
	help
	  Run U-Boot on AndeStar V5 platforms and use some specific features
	  which are provided by Andes Technology AndeStar V5 families.

if RISCV_NDS

config RISCV_NDS_CACHE
	bool "AndeStar V5 families specific cache support"
	help
	  Provide Andes Technology AndeStar V5 families specific cache support.

endif
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> 2018-11-07 10:34:06 +09:00			`config RISCV_NDS`
riscv: ax25: Hide the ax25-specific Kconfig option There is no need to expose RISCV_NDS to the Kconfig menu as it is an ax25-specific option. Introduce a dedicated Kconfig option for the cache ops of ax25 platform and use that to guard the cache ops. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com> 2018-12-12 23:12:28 +09:00			`bool`
riscv: cache: Implement i/dcache [status, enable, disable] AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> 2018-11-07 10:34:06 +09:00			`help`
riscv: ax25: Hide the ax25-specific Kconfig option There is no need to expose RISCV_NDS to the Kconfig menu as it is an ax25-specific option. Introduce a dedicated Kconfig option for the cache ops of ax25 platform and use that to guard the cache ops. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com> 2018-12-12 23:12:28 +09:00			`Run U-Boot on AndeStar V5 platforms and use some specific features`
			`which are provided by Andes Technology AndeStar V5 families.`

			`if RISCV_NDS`

			`config RISCV_NDS_CACHE`
			`bool "AndeStar V5 families specific cache support"`
			`help`
			`Provide Andes Technology AndeStar V5 families specific cache support.`

			`endif`