2018-05-07 06:58:06 +09:00
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// SPDX-License-Identifier: GPL-2.0+
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2015-03-06 04:25:25 +09:00
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/*
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* Copyright (c) 2014 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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2020-05-11 02:40:02 +09:00
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#include <init.h>
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2020-05-11 02:40:05 +09:00
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#include <log.h>
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2020-02-03 23:36:16 +09:00
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#include <malloc.h>
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2015-03-06 04:25:25 +09:00
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#include <pci.h>
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2015-11-30 05:18:03 +09:00
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#include <asm/io.h>
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2015-03-06 04:25:25 +09:00
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#include <dm/device-internal.h>
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2017-05-19 11:09:51 +09:00
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#include <dm/lists.h>
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2015-08-20 22:40:23 +09:00
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#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
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2019-08-25 05:19:05 +09:00
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#include <asm/fsp/fsp_support.h>
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2015-08-20 22:40:23 +09:00
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#endif
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2020-05-11 02:40:11 +09:00
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#include <linux/delay.h>
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2015-11-30 05:17:49 +09:00
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#include "pci_internal.h"
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2015-03-06 04:25:25 +09:00
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DECLARE_GLOBAL_DATA_PTR;
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2016-01-19 12:19:14 +09:00
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int pci_get_bus(int busnum, struct udevice **busp)
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2015-09-01 09:55:35 +09:00
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{
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int ret;
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ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
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/* Since buses may not be numbered yet try a little harder with bus 0 */
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if (ret == -ENODEV) {
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2016-02-12 05:23:26 +09:00
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ret = uclass_first_device_err(UCLASS_PCI, busp);
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2015-09-01 09:55:35 +09:00
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if (ret)
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return ret;
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ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
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}
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return ret;
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}
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2015-11-20 12:27:00 +09:00
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struct udevice *pci_get_controller(struct udevice *dev)
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{
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while (device_is_on_pci_bus(dev))
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dev = dev->parent;
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return dev;
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}
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2020-01-28 00:49:38 +09:00
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pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
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2015-07-07 07:47:46 +09:00
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{
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struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
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struct udevice *bus = dev->parent;
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2019-12-30 13:19:14 +09:00
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/*
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* This error indicates that @dev is a device on an unprobed PCI bus.
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* The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
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* will produce a bad BDF>
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*
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* A common cause of this problem is that this function is called in the
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* ofdata_to_platdata() method of @dev. Accessing the PCI bus in that
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* method is not allowed, since it has not yet been probed. To fix this,
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* move that access to the probe() method of @dev instead.
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*/
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if (!device_active(bus))
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log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
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bus->name);
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2015-07-07 07:47:46 +09:00
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return PCI_ADD_BUS(bus->seq, pplat->devfn);
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}
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2015-03-06 04:25:25 +09:00
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/**
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* pci_get_bus_max() - returns the bus number of the last active bus
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*
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* @return last bus number, or -1 if no active buses
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*/
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static int pci_get_bus_max(void)
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{
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struct udevice *bus;
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struct uclass *uc;
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int ret = -1;
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ret = uclass_get(UCLASS_PCI, &uc);
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uclass_foreach_dev(bus, uc) {
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if (bus->seq > ret)
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ret = bus->seq;
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}
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debug("%s: ret=%d\n", __func__, ret);
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return ret;
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}
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int pci_last_busno(void)
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{
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2015-10-01 16:36:01 +09:00
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return pci_get_bus_max();
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2015-03-06 04:25:25 +09:00
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}
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int pci_get_ff(enum pci_size_t size)
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{
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switch (size) {
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case PCI_SIZE_8:
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return 0xff;
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case PCI_SIZE_16:
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return 0xffff;
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default:
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return 0xffffffff;
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}
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}
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2018-10-11 04:27:06 +09:00
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static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
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ofnode *rnode)
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{
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struct fdt_pci_addr addr;
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ofnode node;
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int ret;
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dev_for_each_subnode(node, bus) {
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ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
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&addr);
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if (ret)
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continue;
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if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
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continue;
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*rnode = node;
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break;
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}
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};
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2020-01-28 00:49:37 +09:00
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int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
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2015-03-06 04:25:25 +09:00
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struct udevice **devp)
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{
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struct udevice *dev;
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for (device_find_first_child(bus, &dev);
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dev;
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device_find_next_child(&dev)) {
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struct pci_child_platdata *pplat;
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pplat = dev_get_parent_platdata(dev);
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if (pplat && pplat->devfn == find_devfn) {
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*devp = dev;
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return 0;
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}
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}
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return -ENODEV;
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}
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2015-11-30 05:17:48 +09:00
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int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
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2015-03-06 04:25:25 +09:00
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{
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struct udevice *bus;
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int ret;
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2015-09-01 09:55:35 +09:00
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ret = pci_get_bus(PCI_BUS(bdf), &bus);
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2015-03-06 04:25:25 +09:00
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if (ret)
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return ret;
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return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
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}
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static int pci_device_matches_ids(struct udevice *dev,
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struct pci_device_id *ids)
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{
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struct pci_child_platdata *pplat;
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int i;
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pplat = dev_get_parent_platdata(dev);
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if (!pplat)
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return -EINVAL;
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for (i = 0; ids[i].vendor != 0; i++) {
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if (pplat->vendor == ids[i].vendor &&
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pplat->device == ids[i].device)
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return i;
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}
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return -EINVAL;
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}
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int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
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int *indexp, struct udevice **devp)
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{
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struct udevice *dev;
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/* Scan all devices on this bus */
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for (device_find_first_child(bus, &dev);
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dev;
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device_find_next_child(&dev)) {
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if (pci_device_matches_ids(dev, ids) >= 0) {
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if ((*indexp)-- <= 0) {
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*devp = dev;
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return 0;
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}
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}
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}
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return -ENODEV;
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}
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int pci_find_device_id(struct pci_device_id *ids, int index,
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struct udevice **devp)
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{
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struct udevice *bus;
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/* Scan all known buses */
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for (uclass_first_device(UCLASS_PCI, &bus);
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bus;
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uclass_next_device(&bus)) {
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if (!pci_bus_find_devices(bus, ids, &index, devp))
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return 0;
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}
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*devp = NULL;
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return -ENODEV;
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}
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2015-11-30 05:17:50 +09:00
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static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
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unsigned int device, int *indexp,
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struct udevice **devp)
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{
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struct pci_child_platdata *pplat;
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struct udevice *dev;
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for (device_find_first_child(bus, &dev);
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dev;
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device_find_next_child(&dev)) {
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pplat = dev_get_parent_platdata(dev);
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if (pplat->vendor == vendor && pplat->device == device) {
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if (!(*indexp)--) {
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*devp = dev;
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return 0;
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}
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}
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}
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return -ENODEV;
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}
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int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
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struct udevice **devp)
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{
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struct udevice *bus;
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/* Scan all known buses */
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for (uclass_first_device(UCLASS_PCI, &bus);
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bus;
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uclass_next_device(&bus)) {
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if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
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return device_probe(*devp);
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}
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*devp = NULL;
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return -ENODEV;
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}
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2015-11-30 05:17:52 +09:00
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int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
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{
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struct udevice *dev;
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/* Scan all known buses */
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for (pci_find_first_device(&dev);
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dev;
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pci_find_next_device(&dev)) {
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struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
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if (pplat->class == find_class && !index--) {
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*devp = dev;
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return device_probe(*devp);
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}
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}
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*devp = NULL;
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return -ENODEV;
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}
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2015-03-06 04:25:25 +09:00
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int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
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unsigned long value, enum pci_size_t size)
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{
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struct dm_pci_ops *ops;
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ops = pci_get_ops(bus);
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if (!ops->write_config)
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return -ENOSYS;
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return ops->write_config(bus, bdf, offset, value, size);
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}
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2016-03-07 11:27:52 +09:00
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int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
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u32 clr, u32 set)
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{
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ulong val;
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int ret;
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ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
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if (ret)
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return ret;
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val &= ~clr;
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val |= set;
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return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
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}
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2015-03-06 04:25:25 +09:00
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int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
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enum pci_size_t size)
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{
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struct udevice *bus;
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int ret;
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2015-09-01 09:55:35 +09:00
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ret = pci_get_bus(PCI_BUS(bdf), &bus);
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2015-03-06 04:25:25 +09:00
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if (ret)
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return ret;
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2015-07-19 01:20:04 +09:00
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return pci_bus_write_config(bus, bdf, offset, value, size);
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2015-03-06 04:25:25 +09:00
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}
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2015-08-10 22:05:03 +09:00
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int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
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enum pci_size_t size)
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{
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struct udevice *bus;
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2015-09-11 19:24:34 +09:00
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for (bus = dev; device_is_on_pci_bus(bus);)
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2015-08-10 22:05:03 +09:00
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bus = bus->parent;
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2015-11-30 05:17:47 +09:00
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return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
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size);
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2015-08-10 22:05:03 +09:00
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}
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2015-03-06 04:25:25 +09:00
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int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
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{
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return pci_write_config(bdf, offset, value, PCI_SIZE_32);
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}
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int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
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{
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return pci_write_config(bdf, offset, value, PCI_SIZE_16);
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}
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int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
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{
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return pci_write_config(bdf, offset, value, PCI_SIZE_8);
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}
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2015-08-10 22:05:03 +09:00
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int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
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{
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return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
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}
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int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
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{
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return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
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}
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int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
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{
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|
|
return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
|
|
|
|
}
|
|
|
|
|
2020-01-28 00:49:38 +09:00
|
|
|
int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
|
2015-03-06 04:25:25 +09:00
|
|
|
unsigned long *valuep, enum pci_size_t size)
|
|
|
|
{
|
|
|
|
struct dm_pci_ops *ops;
|
|
|
|
|
|
|
|
ops = pci_get_ops(bus);
|
|
|
|
if (!ops->read_config)
|
|
|
|
return -ENOSYS;
|
|
|
|
return ops->read_config(bus, bdf, offset, valuep, size);
|
|
|
|
}
|
|
|
|
|
|
|
|
int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
|
|
|
|
enum pci_size_t size)
|
|
|
|
{
|
|
|
|
struct udevice *bus;
|
|
|
|
int ret;
|
|
|
|
|
2015-09-01 09:55:35 +09:00
|
|
|
ret = pci_get_bus(PCI_BUS(bdf), &bus);
|
2015-03-06 04:25:25 +09:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2015-07-19 01:20:04 +09:00
|
|
|
return pci_bus_read_config(bus, bdf, offset, valuep, size);
|
2015-03-06 04:25:25 +09:00
|
|
|
}
|
|
|
|
|
2020-01-28 00:49:38 +09:00
|
|
|
int dm_pci_read_config(const struct udevice *dev, int offset,
|
|
|
|
unsigned long *valuep, enum pci_size_t size)
|
2015-08-10 22:05:03 +09:00
|
|
|
{
|
2020-01-28 00:49:38 +09:00
|
|
|
const struct udevice *bus;
|
2015-08-10 22:05:03 +09:00
|
|
|
|
2015-09-11 19:24:34 +09:00
|
|
|
for (bus = dev; device_is_on_pci_bus(bus);)
|
2015-08-10 22:05:03 +09:00
|
|
|
bus = bus->parent;
|
2015-11-30 05:17:47 +09:00
|
|
|
return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
|
2015-08-10 22:05:03 +09:00
|
|
|
size);
|
|
|
|
}
|
|
|
|
|
2015-03-06 04:25:25 +09:00
|
|
|
int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
|
|
|
|
{
|
|
|
|
unsigned long value;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
*valuep = value;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
|
|
|
|
{
|
|
|
|
unsigned long value;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
*valuep = value;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
|
|
|
|
{
|
|
|
|
unsigned long value;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
*valuep = value;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-01-28 00:49:38 +09:00
|
|
|
int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
|
2015-08-10 22:05:03 +09:00
|
|
|
{
|
|
|
|
unsigned long value;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
*valuep = value;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-01-28 00:49:38 +09:00
|
|
|
int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
|
2015-08-10 22:05:03 +09:00
|
|
|
{
|
|
|
|
unsigned long value;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
*valuep = value;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-01-28 00:49:38 +09:00
|
|
|
int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
|
2015-08-10 22:05:03 +09:00
|
|
|
{
|
|
|
|
unsigned long value;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
*valuep = value;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-03-07 11:27:52 +09:00
|
|
|
int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
|
|
|
|
{
|
|
|
|
u8 val;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = dm_pci_read_config8(dev, offset, &val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
val &= ~clr;
|
|
|
|
val |= set;
|
|
|
|
|
|
|
|
return dm_pci_write_config8(dev, offset, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
|
|
|
|
{
|
|
|
|
u16 val;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = dm_pci_read_config16(dev, offset, &val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
val &= ~clr;
|
|
|
|
val |= set;
|
|
|
|
|
|
|
|
return dm_pci_write_config16(dev, offset, val);
|
|
|
|
}
|
|
|
|
|
|
|
|
int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = dm_pci_read_config32(dev, offset, &val);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
val &= ~clr;
|
|
|
|
val |= set;
|
|
|
|
|
|
|
|
return dm_pci_write_config32(dev, offset, val);
|
|
|
|
}
|
|
|
|
|
2015-10-01 16:36:02 +09:00
|
|
|
static void set_vga_bridge_bits(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct udevice *parent = dev->parent;
|
|
|
|
u16 bc;
|
|
|
|
|
|
|
|
while (parent->seq != 0) {
|
|
|
|
dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
|
|
|
|
bc |= PCI_BRIDGE_CTL_VGA;
|
|
|
|
dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
|
|
|
|
parent = parent->parent;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-03-06 04:25:25 +09:00
|
|
|
int pci_auto_config_devices(struct udevice *bus)
|
|
|
|
{
|
|
|
|
struct pci_controller *hose = bus->uclass_priv;
|
2015-10-01 16:36:02 +09:00
|
|
|
struct pci_child_platdata *pplat;
|
2015-03-06 04:25:25 +09:00
|
|
|
unsigned int sub_bus;
|
|
|
|
struct udevice *dev;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
sub_bus = bus->seq;
|
|
|
|
debug("%s: start\n", __func__);
|
|
|
|
pciauto_config_init(hose);
|
|
|
|
for (ret = device_find_first_child(bus, &dev);
|
|
|
|
!ret && dev;
|
|
|
|
ret = device_find_next_child(&dev)) {
|
|
|
|
unsigned int max_bus;
|
2015-09-09 08:52:47 +09:00
|
|
|
int ret;
|
2015-03-06 04:25:25 +09:00
|
|
|
|
|
|
|
debug("%s: device %s\n", __func__, dev->name);
|
2020-04-09 07:57:26 +09:00
|
|
|
if (dev_read_bool(dev, "pci,no-autoconfig"))
|
|
|
|
continue;
|
2015-11-30 05:17:49 +09:00
|
|
|
ret = dm_pciauto_config_device(dev);
|
2015-09-09 08:52:47 +09:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
max_bus = ret;
|
2015-03-06 04:25:25 +09:00
|
|
|
sub_bus = max(sub_bus, max_bus);
|
2015-10-01 16:36:02 +09:00
|
|
|
|
|
|
|
pplat = dev_get_parent_platdata(dev);
|
|
|
|
if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
|
|
|
|
set_vga_bridge_bits(dev);
|
2015-03-06 04:25:25 +09:00
|
|
|
}
|
|
|
|
debug("%s: done\n", __func__);
|
|
|
|
|
|
|
|
return sub_bus;
|
|
|
|
}
|
|
|
|
|
2017-09-20 05:18:03 +09:00
|
|
|
int pci_generic_mmap_write_config(
|
2020-01-28 00:49:37 +09:00
|
|
|
const struct udevice *bus,
|
|
|
|
int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
|
|
|
|
void **addrp),
|
2017-09-20 05:18:03 +09:00
|
|
|
pci_dev_t bdf,
|
|
|
|
uint offset,
|
|
|
|
ulong value,
|
|
|
|
enum pci_size_t size)
|
|
|
|
{
|
|
|
|
void *address;
|
|
|
|
|
|
|
|
if (addr_f(bus, bdf, offset, &address) < 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
switch (size) {
|
|
|
|
case PCI_SIZE_8:
|
|
|
|
writeb(value, address);
|
|
|
|
return 0;
|
|
|
|
case PCI_SIZE_16:
|
|
|
|
writew(value, address);
|
|
|
|
return 0;
|
|
|
|
case PCI_SIZE_32:
|
|
|
|
writel(value, address);
|
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int pci_generic_mmap_read_config(
|
2020-01-28 00:49:37 +09:00
|
|
|
const struct udevice *bus,
|
|
|
|
int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
|
|
|
|
void **addrp),
|
2017-09-20 05:18:03 +09:00
|
|
|
pci_dev_t bdf,
|
|
|
|
uint offset,
|
|
|
|
ulong *valuep,
|
|
|
|
enum pci_size_t size)
|
|
|
|
{
|
|
|
|
void *address;
|
|
|
|
|
|
|
|
if (addr_f(bus, bdf, offset, &address) < 0) {
|
|
|
|
*valuep = pci_get_ff(size);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (size) {
|
|
|
|
case PCI_SIZE_8:
|
|
|
|
*valuep = readb(address);
|
|
|
|
return 0;
|
|
|
|
case PCI_SIZE_16:
|
|
|
|
*valuep = readw(address);
|
|
|
|
return 0;
|
|
|
|
case PCI_SIZE_32:
|
|
|
|
*valuep = readl(address);
|
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-11-30 05:17:49 +09:00
|
|
|
int dm_pci_hose_probe_bus(struct udevice *bus)
|
2015-03-06 04:25:25 +09:00
|
|
|
{
|
|
|
|
int sub_bus;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
debug("%s\n", __func__);
|
|
|
|
|
|
|
|
sub_bus = pci_get_bus_max() + 1;
|
|
|
|
debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
|
2015-11-30 05:17:49 +09:00
|
|
|
dm_pciauto_prescan_setup_bridge(bus, sub_bus);
|
2015-03-06 04:25:25 +09:00
|
|
|
|
|
|
|
ret = device_probe(bus);
|
|
|
|
if (ret) {
|
2015-09-09 08:52:48 +09:00
|
|
|
debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
|
2015-03-06 04:25:25 +09:00
|
|
|
ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (sub_bus != bus->seq) {
|
|
|
|
printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
|
|
|
|
__func__, bus->name, bus->seq, sub_bus);
|
|
|
|
return -EPIPE;
|
|
|
|
}
|
|
|
|
sub_bus = pci_get_bus_max();
|
2015-11-30 05:17:49 +09:00
|
|
|
dm_pciauto_postscan_setup_bridge(bus, sub_bus);
|
2015-03-06 04:25:25 +09:00
|
|
|
|
|
|
|
return sub_bus;
|
|
|
|
}
|
|
|
|
|
2015-07-07 07:47:44 +09:00
|
|
|
/**
|
|
|
|
* pci_match_one_device - Tell if a PCI device structure has a matching
|
|
|
|
* PCI device id structure
|
|
|
|
* @id: single PCI device id structure to match
|
2017-03-22 17:07:24 +09:00
|
|
|
* @find: the PCI device id structure to match against
|
2015-07-07 07:47:44 +09:00
|
|
|
*
|
2017-03-22 17:07:24 +09:00
|
|
|
* Returns true if the finding pci_device_id structure matched or false if
|
|
|
|
* there is no match.
|
2015-07-07 07:47:44 +09:00
|
|
|
*/
|
|
|
|
static bool pci_match_one_id(const struct pci_device_id *id,
|
|
|
|
const struct pci_device_id *find)
|
|
|
|
{
|
|
|
|
if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
|
|
|
|
(id->device == PCI_ANY_ID || id->device == find->device) &&
|
|
|
|
(id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
|
|
|
|
(id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
|
|
|
|
!((id->class ^ find->class) & id->class_mask))
|
|
|
|
return true;
|
|
|
|
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* pci_find_and_bind_driver() - Find and bind the right PCI driver
|
|
|
|
*
|
|
|
|
* This only looks at certain fields in the descriptor.
|
2015-09-09 08:52:49 +09:00
|
|
|
*
|
|
|
|
* @parent: Parent bus
|
|
|
|
* @find_id: Specification of the driver to find
|
|
|
|
* @bdf: Bus/device/function addreess - see PCI_BDF()
|
|
|
|
* @devp: Returns a pointer to the device created
|
|
|
|
* @return 0 if OK, -EPERM if the device is not needed before relocation and
|
|
|
|
* therefore was not created, other -ve value on error
|
2015-07-07 07:47:44 +09:00
|
|
|
*/
|
|
|
|
static int pci_find_and_bind_driver(struct udevice *parent,
|
2015-09-09 08:52:49 +09:00
|
|
|
struct pci_device_id *find_id,
|
|
|
|
pci_dev_t bdf, struct udevice **devp)
|
2015-07-07 07:47:44 +09:00
|
|
|
{
|
|
|
|
struct pci_driver_entry *start, *entry;
|
2018-10-11 04:27:06 +09:00
|
|
|
ofnode node = ofnode_null();
|
2015-07-07 07:47:44 +09:00
|
|
|
const char *drv;
|
|
|
|
int n_ents;
|
|
|
|
int ret;
|
|
|
|
char name[30], *str;
|
2015-08-20 22:40:17 +09:00
|
|
|
bool bridge;
|
2015-07-07 07:47:44 +09:00
|
|
|
|
|
|
|
*devp = NULL;
|
|
|
|
|
|
|
|
debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
|
|
|
|
find_id->vendor, find_id->device);
|
2018-10-11 04:27:06 +09:00
|
|
|
|
|
|
|
/* Determine optional OF node */
|
|
|
|
pci_dev_find_ofnode(parent, bdf, &node);
|
|
|
|
|
2019-12-02 01:45:18 +09:00
|
|
|
if (ofnode_valid(node) && !ofnode_is_available(node)) {
|
|
|
|
debug("%s: Ignoring disabled device\n", __func__);
|
|
|
|
return -EPERM;
|
|
|
|
}
|
|
|
|
|
2015-07-07 07:47:44 +09:00
|
|
|
start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
|
|
|
|
n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
|
|
|
|
for (entry = start; entry != start + n_ents; entry++) {
|
|
|
|
const struct pci_device_id *id;
|
|
|
|
struct udevice *dev;
|
|
|
|
const struct driver *drv;
|
|
|
|
|
|
|
|
for (id = entry->match;
|
|
|
|
id->vendor || id->subvendor || id->class_mask;
|
|
|
|
id++) {
|
|
|
|
if (!pci_match_one_id(id, find_id))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
drv = entry->driver;
|
2015-08-20 22:40:17 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* In the pre-relocation phase, we only bind devices
|
|
|
|
* whose driver has the DM_FLAG_PRE_RELOC set, to save
|
|
|
|
* precious memory space as on some platforms as that
|
|
|
|
* space is pretty limited (ie: using Cache As RAM).
|
|
|
|
*/
|
|
|
|
if (!(gd->flags & GD_FLG_RELOC) &&
|
|
|
|
!(drv->flags & DM_FLAG_PRE_RELOC))
|
2015-09-09 08:52:49 +09:00
|
|
|
return -EPERM;
|
2015-08-20 22:40:17 +09:00
|
|
|
|
2015-07-07 07:47:44 +09:00
|
|
|
/*
|
|
|
|
* We could pass the descriptor to the driver as
|
|
|
|
* platdata (instead of NULL) and allow its bind()
|
|
|
|
* method to return -ENOENT if it doesn't support this
|
|
|
|
* device. That way we could continue the search to
|
|
|
|
* find another driver. For now this doesn't seem
|
|
|
|
* necesssary, so just bind the first match.
|
|
|
|
*/
|
2018-10-11 04:27:06 +09:00
|
|
|
ret = device_bind_ofnode(parent, drv, drv->name, NULL,
|
|
|
|
node, &dev);
|
2015-07-07 07:47:44 +09:00
|
|
|
if (ret)
|
|
|
|
goto error;
|
|
|
|
debug("%s: Match found: %s\n", __func__, drv->name);
|
2018-08-03 17:14:44 +09:00
|
|
|
dev->driver_data = id->driver_data;
|
2015-07-07 07:47:44 +09:00
|
|
|
*devp = dev;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-08-20 22:40:17 +09:00
|
|
|
bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
|
|
|
|
/*
|
|
|
|
* In the pre-relocation phase, we only bind bridge devices to save
|
|
|
|
* precious memory space as on some platforms as that space is pretty
|
|
|
|
* limited (ie: using Cache As RAM).
|
|
|
|
*/
|
|
|
|
if (!(gd->flags & GD_FLG_RELOC) && !bridge)
|
2015-09-09 08:52:49 +09:00
|
|
|
return -EPERM;
|
2015-08-20 22:40:17 +09:00
|
|
|
|
2015-07-07 07:47:44 +09:00
|
|
|
/* Bind a generic driver so that the device can be used */
|
2015-07-19 01:20:04 +09:00
|
|
|
sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
|
|
|
|
PCI_FUNC(bdf));
|
2015-07-07 07:47:44 +09:00
|
|
|
str = strdup(name);
|
|
|
|
if (!str)
|
|
|
|
return -ENOMEM;
|
2015-08-20 22:40:17 +09:00
|
|
|
drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
|
|
|
|
|
2018-10-11 04:27:06 +09:00
|
|
|
ret = device_bind_driver_to_node(parent, drv, str, node, devp);
|
2015-07-07 07:47:44 +09:00
|
|
|
if (ret) {
|
2015-09-09 08:52:48 +09:00
|
|
|
debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
|
2017-05-09 03:40:16 +09:00
|
|
|
free(str);
|
2015-07-07 07:47:44 +09:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
debug("%s: No match found: bound generic driver instead\n", __func__);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
error:
|
|
|
|
debug("%s: No match found: error %d\n", __func__, ret);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2015-03-06 04:25:25 +09:00
|
|
|
int pci_bind_bus_devices(struct udevice *bus)
|
|
|
|
{
|
|
|
|
ulong vendor, device;
|
|
|
|
ulong header_type;
|
2015-07-19 01:20:04 +09:00
|
|
|
pci_dev_t bdf, end;
|
2015-03-06 04:25:25 +09:00
|
|
|
bool found_multi;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
found_multi = false;
|
2015-07-19 01:20:04 +09:00
|
|
|
end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
|
|
|
|
PCI_MAX_PCI_FUNCTIONS - 1);
|
2016-04-25 15:41:01 +09:00
|
|
|
for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
|
2015-07-19 01:20:04 +09:00
|
|
|
bdf += PCI_BDF(0, 0, 1)) {
|
2015-03-06 04:25:25 +09:00
|
|
|
struct pci_child_platdata *pplat;
|
|
|
|
struct udevice *dev;
|
|
|
|
ulong class;
|
|
|
|
|
2018-08-03 17:14:37 +09:00
|
|
|
if (!PCI_FUNC(bdf))
|
|
|
|
found_multi = false;
|
2015-07-19 01:20:04 +09:00
|
|
|
if (PCI_FUNC(bdf) && !found_multi)
|
2015-03-06 04:25:25 +09:00
|
|
|
continue;
|
2018-10-08 17:35:47 +09:00
|
|
|
|
2015-03-06 04:25:25 +09:00
|
|
|
/* Check only the first access, we don't expect problems */
|
2018-10-08 17:35:47 +09:00
|
|
|
ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
|
|
|
|
PCI_SIZE_16);
|
2015-03-06 04:25:25 +09:00
|
|
|
if (ret)
|
|
|
|
goto error;
|
2018-10-08 17:35:47 +09:00
|
|
|
|
2015-03-06 04:25:25 +09:00
|
|
|
if (vendor == 0xffff || vendor == 0x0000)
|
|
|
|
continue;
|
|
|
|
|
2018-10-08 17:35:47 +09:00
|
|
|
pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
|
|
|
|
&header_type, PCI_SIZE_8);
|
|
|
|
|
2015-07-19 01:20:04 +09:00
|
|
|
if (!PCI_FUNC(bdf))
|
2015-03-06 04:25:25 +09:00
|
|
|
found_multi = header_type & 0x80;
|
|
|
|
|
2019-09-25 23:56:12 +09:00
|
|
|
debug("%s: bus %d/%s: found device %x, function %d", __func__,
|
2015-07-19 01:20:04 +09:00
|
|
|
bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
|
|
|
|
pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
|
2015-03-06 04:25:25 +09:00
|
|
|
PCI_SIZE_16);
|
2015-07-19 01:20:04 +09:00
|
|
|
pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
|
2015-07-07 07:47:44 +09:00
|
|
|
PCI_SIZE_32);
|
|
|
|
class >>= 8;
|
2015-03-06 04:25:25 +09:00
|
|
|
|
|
|
|
/* Find this device in the device tree */
|
2015-07-19 01:20:04 +09:00
|
|
|
ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
|
2019-09-25 23:56:12 +09:00
|
|
|
debug(": find ret=%d\n", ret);
|
2015-03-06 04:25:25 +09:00
|
|
|
|
2015-11-30 05:18:09 +09:00
|
|
|
/* If nothing in the device tree, bind a device */
|
2015-03-06 04:25:25 +09:00
|
|
|
if (ret == -ENODEV) {
|
2015-07-07 07:47:44 +09:00
|
|
|
struct pci_device_id find_id;
|
|
|
|
ulong val;
|
|
|
|
|
|
|
|
memset(&find_id, '\0', sizeof(find_id));
|
|
|
|
find_id.vendor = vendor;
|
|
|
|
find_id.device = device;
|
|
|
|
find_id.class = class;
|
|
|
|
if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
|
2015-07-19 01:20:04 +09:00
|
|
|
pci_bus_read_config(bus, bdf,
|
2015-07-07 07:47:44 +09:00
|
|
|
PCI_SUBSYSTEM_VENDOR_ID,
|
|
|
|
&val, PCI_SIZE_32);
|
|
|
|
find_id.subvendor = val & 0xffff;
|
|
|
|
find_id.subdevice = val >> 16;
|
|
|
|
}
|
2015-07-19 01:20:04 +09:00
|
|
|
ret = pci_find_and_bind_driver(bus, &find_id, bdf,
|
2015-07-07 07:47:44 +09:00
|
|
|
&dev);
|
2015-03-06 04:25:25 +09:00
|
|
|
}
|
2015-09-09 08:52:49 +09:00
|
|
|
if (ret == -EPERM)
|
|
|
|
continue;
|
|
|
|
else if (ret)
|
2015-03-06 04:25:25 +09:00
|
|
|
return ret;
|
|
|
|
|
|
|
|
/* Update the platform data */
|
2015-09-09 08:52:49 +09:00
|
|
|
pplat = dev_get_parent_platdata(dev);
|
|
|
|
pplat->devfn = PCI_MASK_BUS(bdf);
|
|
|
|
pplat->vendor = vendor;
|
|
|
|
pplat->device = device;
|
|
|
|
pplat->class = class;
|
2015-03-06 04:25:25 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
error:
|
|
|
|
printf("Cannot read bus configuration: %d\n", ret);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-06-10 22:25:05 +09:00
|
|
|
static void decode_regions(struct pci_controller *hose, ofnode parent_node,
|
|
|
|
ofnode node)
|
2015-03-06 04:25:25 +09:00
|
|
|
{
|
|
|
|
int pci_addr_cells, addr_cells, size_cells;
|
|
|
|
int cells_per_record;
|
|
|
|
const u32 *prop;
|
|
|
|
int len;
|
|
|
|
int i;
|
|
|
|
|
2017-06-22 16:54:05 +09:00
|
|
|
prop = ofnode_get_property(node, "ranges", &len);
|
2018-06-10 22:25:05 +09:00
|
|
|
if (!prop) {
|
|
|
|
debug("%s: Cannot decode regions\n", __func__);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2017-06-12 21:21:31 +09:00
|
|
|
pci_addr_cells = ofnode_read_simple_addr_cells(node);
|
|
|
|
addr_cells = ofnode_read_simple_addr_cells(parent_node);
|
|
|
|
size_cells = ofnode_read_simple_size_cells(node);
|
2015-03-06 04:25:25 +09:00
|
|
|
|
|
|
|
/* PCI addresses are always 3-cells */
|
|
|
|
len /= sizeof(u32);
|
|
|
|
cells_per_record = pci_addr_cells + addr_cells + size_cells;
|
|
|
|
hose->region_count = 0;
|
|
|
|
debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
|
|
|
|
cells_per_record);
|
|
|
|
for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
|
|
|
|
u64 pci_addr, addr, size;
|
|
|
|
int space_code;
|
|
|
|
u32 flags;
|
|
|
|
int type;
|
2015-11-20 12:26:58 +09:00
|
|
|
int pos;
|
2015-03-06 04:25:25 +09:00
|
|
|
|
|
|
|
if (len < cells_per_record)
|
|
|
|
break;
|
|
|
|
flags = fdt32_to_cpu(prop[0]);
|
|
|
|
space_code = (flags >> 24) & 3;
|
|
|
|
pci_addr = fdtdec_get_number(prop + 1, 2);
|
|
|
|
prop += pci_addr_cells;
|
|
|
|
addr = fdtdec_get_number(prop, addr_cells);
|
|
|
|
prop += addr_cells;
|
|
|
|
size = fdtdec_get_number(prop, size_cells);
|
|
|
|
prop += size_cells;
|
2018-08-06 20:47:40 +09:00
|
|
|
debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
|
|
|
|
__func__, hose->region_count, pci_addr, addr, size, space_code);
|
2015-03-06 04:25:25 +09:00
|
|
|
if (space_code & 2) {
|
|
|
|
type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
|
|
|
|
PCI_REGION_MEM;
|
|
|
|
} else if (space_code & 1) {
|
|
|
|
type = PCI_REGION_IO;
|
|
|
|
} else {
|
|
|
|
continue;
|
|
|
|
}
|
2018-05-15 00:47:50 +09:00
|
|
|
|
|
|
|
if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
|
|
|
|
type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
|
|
|
|
debug(" - beyond the 32-bit boundary, ignoring\n");
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2015-11-20 12:26:58 +09:00
|
|
|
pos = -1;
|
|
|
|
for (i = 0; i < hose->region_count; i++) {
|
|
|
|
if (hose->regions[i].flags == type)
|
|
|
|
pos = i;
|
|
|
|
}
|
|
|
|
if (pos == -1)
|
|
|
|
pos = hose->region_count++;
|
|
|
|
debug(" - type=%d, pos=%d\n", type, pos);
|
|
|
|
pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
|
2015-03-06 04:25:25 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Add a region for our local memory */
|
2018-02-15 16:59:53 +09:00
|
|
|
#ifdef CONFIG_NR_DRAM_BANKS
|
2020-06-26 15:13:33 +09:00
|
|
|
struct bd_info *bd = gd->bd;
|
2018-02-15 16:59:53 +09:00
|
|
|
|
2018-03-27 16:46:05 +09:00
|
|
|
if (!bd)
|
2018-06-10 22:25:05 +09:00
|
|
|
return;
|
2018-03-27 16:46:05 +09:00
|
|
|
|
2018-02-15 16:59:53 +09:00
|
|
|
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
|
2019-03-16 00:32:32 +09:00
|
|
|
if (hose->region_count == MAX_PCI_REGIONS) {
|
|
|
|
pr_err("maximum number of regions parsed, aborting\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2018-02-15 16:59:53 +09:00
|
|
|
if (bd->bi_dram[i].size) {
|
|
|
|
pci_set_region(hose->regions + hose->region_count++,
|
|
|
|
bd->bi_dram[i].start,
|
|
|
|
bd->bi_dram[i].start,
|
|
|
|
bd->bi_dram[i].size,
|
|
|
|
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
phys_addr_t base = 0, size;
|
|
|
|
|
2015-11-20 12:26:57 +09:00
|
|
|
size = gd->ram_size;
|
|
|
|
#ifdef CONFIG_SYS_SDRAM_BASE
|
|
|
|
base = CONFIG_SYS_SDRAM_BASE;
|
|
|
|
#endif
|
|
|
|
if (gd->pci_ram_top && gd->pci_ram_top < base + size)
|
|
|
|
size = gd->pci_ram_top - base;
|
2018-03-27 16:46:06 +09:00
|
|
|
if (size)
|
|
|
|
pci_set_region(hose->regions + hose->region_count++, base,
|
|
|
|
base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
|
2018-02-15 16:59:53 +09:00
|
|
|
#endif
|
2015-03-06 04:25:25 +09:00
|
|
|
|
2018-06-10 22:25:05 +09:00
|
|
|
return;
|
2015-03-06 04:25:25 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static int pci_uclass_pre_probe(struct udevice *bus)
|
|
|
|
{
|
|
|
|
struct pci_controller *hose;
|
|
|
|
|
|
|
|
debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
|
|
|
|
bus->parent->name);
|
|
|
|
hose = bus->uclass_priv;
|
|
|
|
|
|
|
|
/* For bridges, use the top-level PCI controller */
|
2016-09-08 15:47:32 +09:00
|
|
|
if (!device_is_on_pci_bus(bus)) {
|
2015-03-06 04:25:25 +09:00
|
|
|
hose->ctlr = bus;
|
2018-06-10 22:25:05 +09:00
|
|
|
decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
|
2015-03-06 04:25:25 +09:00
|
|
|
} else {
|
|
|
|
struct pci_controller *parent_hose;
|
|
|
|
|
|
|
|
parent_hose = dev_get_uclass_priv(bus->parent);
|
|
|
|
hose->ctlr = parent_hose->bus;
|
|
|
|
}
|
|
|
|
hose->bus = bus;
|
|
|
|
hose->first_busno = bus->seq;
|
|
|
|
hose->last_busno = bus->seq;
|
2019-12-07 13:41:37 +09:00
|
|
|
hose->skip_auto_config_until_reloc =
|
|
|
|
dev_read_bool(bus, "u-boot,skip-auto-config-until-reloc");
|
2015-03-06 04:25:25 +09:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pci_uclass_post_probe(struct udevice *bus)
|
|
|
|
{
|
2019-12-07 13:41:37 +09:00
|
|
|
struct pci_controller *hose = dev_get_uclass_priv(bus);
|
2015-03-06 04:25:25 +09:00
|
|
|
int ret;
|
|
|
|
|
|
|
|
debug("%s: probing bus %d\n", __func__, bus->seq);
|
|
|
|
ret = pci_bind_bus_devices(bus);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2020-04-27 00:12:56 +09:00
|
|
|
if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
|
2019-12-07 13:41:37 +09:00
|
|
|
(!hose->skip_auto_config_until_reloc ||
|
|
|
|
(gd->flags & GD_FLG_RELOC))) {
|
|
|
|
ret = pci_auto_config_devices(bus);
|
|
|
|
if (ret < 0)
|
|
|
|
return log_msg_ret("pci auto-config", ret);
|
|
|
|
}
|
2015-03-06 04:25:25 +09:00
|
|
|
|
2015-08-20 22:40:23 +09:00
|
|
|
#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
|
|
|
|
/*
|
|
|
|
* Per Intel FSP specification, we should call FSP notify API to
|
|
|
|
* inform FSP that PCI enumeration has been done so that FSP will
|
|
|
|
* do any necessary initialization as required by the chipset's
|
|
|
|
* BIOS Writer's Guide (BWG).
|
|
|
|
*
|
|
|
|
* Unfortunately we have to put this call here as with driver model,
|
|
|
|
* the enumeration is all done on a lazy basis as needed, so until
|
|
|
|
* something is touched on PCI it won't happen.
|
|
|
|
*
|
|
|
|
* Note we only call this 1) after U-Boot is relocated, and 2)
|
|
|
|
* root bus has finished probing.
|
|
|
|
*/
|
2020-04-27 00:12:56 +09:00
|
|
|
if ((gd->flags & GD_FLG_RELOC) && bus->seq == 0 && ll_boot_init()) {
|
2015-08-20 22:40:23 +09:00
|
|
|
ret = fsp_init_phase_pci();
|
2015-09-09 08:52:47 +09:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
}
|
2015-08-20 22:40:23 +09:00
|
|
|
#endif
|
|
|
|
|
2015-09-09 08:52:47 +09:00
|
|
|
return 0;
|
2015-03-06 04:25:25 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static int pci_uclass_child_post_bind(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct pci_child_platdata *pplat;
|
|
|
|
|
2017-05-19 11:09:51 +09:00
|
|
|
if (!dev_of_valid(dev))
|
2015-03-06 04:25:25 +09:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
pplat = dev_get_parent_platdata(dev);
|
2018-08-03 17:14:36 +09:00
|
|
|
|
|
|
|
/* Extract vendor id and device id if available */
|
|
|
|
ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
|
|
|
|
|
|
|
|
/* Extract the devfn from fdt_pci_addr */
|
2019-01-25 19:52:42 +09:00
|
|
|
pplat->devfn = pci_get_devfn(dev);
|
2015-03-06 04:25:25 +09:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-01-28 00:49:37 +09:00
|
|
|
static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
|
2015-07-19 01:20:04 +09:00
|
|
|
uint offset, ulong *valuep,
|
|
|
|
enum pci_size_t size)
|
2015-03-06 04:25:25 +09:00
|
|
|
{
|
|
|
|
struct pci_controller *hose = bus->uclass_priv;
|
|
|
|
|
|
|
|
return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
|
|
|
|
}
|
|
|
|
|
2015-07-19 01:20:04 +09:00
|
|
|
static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
|
|
|
|
uint offset, ulong value,
|
|
|
|
enum pci_size_t size)
|
2015-03-06 04:25:25 +09:00
|
|
|
{
|
|
|
|
struct pci_controller *hose = bus->uclass_priv;
|
|
|
|
|
|
|
|
return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
|
|
|
|
}
|
|
|
|
|
2015-08-10 22:05:04 +09:00
|
|
|
static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
|
|
|
|
{
|
|
|
|
struct udevice *dev;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Scan through all the PCI controllers. On x86 there will only be one
|
|
|
|
* but that is not necessarily true on other hardware.
|
|
|
|
*/
|
|
|
|
do {
|
|
|
|
device_find_first_child(bus, &dev);
|
|
|
|
if (dev) {
|
|
|
|
*devp = dev;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
ret = uclass_next_device(&bus);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
} while (bus);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int pci_find_next_device(struct udevice **devp)
|
|
|
|
{
|
|
|
|
struct udevice *child = *devp;
|
|
|
|
struct udevice *bus = child->parent;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* First try all the siblings */
|
|
|
|
*devp = NULL;
|
|
|
|
while (child) {
|
|
|
|
device_find_next_child(&child);
|
|
|
|
if (child) {
|
|
|
|
*devp = child;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We ran out of siblings. Try the next bus */
|
|
|
|
ret = uclass_next_device(&bus);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return bus ? skip_to_next_device(bus, devp) : 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int pci_find_first_device(struct udevice **devp)
|
|
|
|
{
|
|
|
|
struct udevice *bus;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
*devp = NULL;
|
|
|
|
ret = uclass_first_device(UCLASS_PCI, &bus);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return skip_to_next_device(bus, devp);
|
|
|
|
}
|
|
|
|
|
2015-11-20 12:26:59 +09:00
|
|
|
ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
|
|
|
|
{
|
|
|
|
switch (size) {
|
|
|
|
case PCI_SIZE_8:
|
|
|
|
return (value >> ((offset & 3) * 8)) & 0xff;
|
|
|
|
case PCI_SIZE_16:
|
|
|
|
return (value >> ((offset & 2) * 8)) & 0xffff;
|
|
|
|
default:
|
|
|
|
return value;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
|
|
|
|
enum pci_size_t size)
|
|
|
|
{
|
|
|
|
uint off_mask;
|
|
|
|
uint val_mask, shift;
|
|
|
|
ulong ldata, mask;
|
|
|
|
|
|
|
|
switch (size) {
|
|
|
|
case PCI_SIZE_8:
|
|
|
|
off_mask = 3;
|
|
|
|
val_mask = 0xff;
|
|
|
|
break;
|
|
|
|
case PCI_SIZE_16:
|
|
|
|
off_mask = 2;
|
|
|
|
val_mask = 0xffff;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return value;
|
|
|
|
}
|
|
|
|
shift = (offset & off_mask) * 8;
|
|
|
|
ldata = (value & val_mask) << shift;
|
|
|
|
mask = val_mask << shift;
|
|
|
|
value = (old & ~mask) | ldata;
|
|
|
|
|
|
|
|
return value;
|
|
|
|
}
|
|
|
|
|
2020-05-12 16:59:49 +09:00
|
|
|
int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
|
|
|
|
{
|
|
|
|
int pci_addr_cells, addr_cells, size_cells;
|
|
|
|
int cells_per_record;
|
|
|
|
const u32 *prop;
|
|
|
|
int len;
|
|
|
|
int i = 0;
|
|
|
|
|
|
|
|
prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
|
|
|
|
if (!prop) {
|
|
|
|
log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
|
|
|
|
dev->name);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
|
|
|
|
addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
|
|
|
|
size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
|
|
|
|
|
|
|
|
/* PCI addresses are always 3-cells */
|
|
|
|
len /= sizeof(u32);
|
|
|
|
cells_per_record = pci_addr_cells + addr_cells + size_cells;
|
|
|
|
debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
|
|
|
|
cells_per_record);
|
|
|
|
|
|
|
|
while (len) {
|
|
|
|
memp->bus_start = fdtdec_get_number(prop + 1, 2);
|
|
|
|
prop += pci_addr_cells;
|
|
|
|
memp->phys_start = fdtdec_get_number(prop, addr_cells);
|
|
|
|
prop += addr_cells;
|
|
|
|
memp->size = fdtdec_get_number(prop, size_cells);
|
|
|
|
prop += size_cells;
|
|
|
|
|
|
|
|
if (i == index)
|
|
|
|
return 0;
|
|
|
|
i++;
|
|
|
|
len -= cells_per_record;
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2015-11-20 12:27:01 +09:00
|
|
|
int pci_get_regions(struct udevice *dev, struct pci_region **iop,
|
|
|
|
struct pci_region **memp, struct pci_region **prefp)
|
|
|
|
{
|
|
|
|
struct udevice *bus = pci_get_controller(dev);
|
|
|
|
struct pci_controller *hose = dev_get_uclass_priv(bus);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
*iop = NULL;
|
|
|
|
*memp = NULL;
|
|
|
|
*prefp = NULL;
|
|
|
|
for (i = 0; i < hose->region_count; i++) {
|
|
|
|
switch (hose->regions[i].flags) {
|
|
|
|
case PCI_REGION_IO:
|
|
|
|
if (!*iop || (*iop)->size < hose->regions[i].size)
|
|
|
|
*iop = hose->regions + i;
|
|
|
|
break;
|
|
|
|
case PCI_REGION_MEM:
|
|
|
|
if (!*memp || (*memp)->size < hose->regions[i].size)
|
|
|
|
*memp = hose->regions + i;
|
|
|
|
break;
|
|
|
|
case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
|
|
|
|
if (!*prefp || (*prefp)->size < hose->regions[i].size)
|
|
|
|
*prefp = hose->regions + i;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
|
|
|
|
}
|
|
|
|
|
2020-01-28 00:49:38 +09:00
|
|
|
u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
|
2015-11-30 05:17:53 +09:00
|
|
|
{
|
|
|
|
u32 addr;
|
|
|
|
int bar;
|
|
|
|
|
|
|
|
bar = PCI_BASE_ADDRESS_0 + barnum * 4;
|
|
|
|
dm_pci_read_config32(dev, bar, &addr);
|
2020-04-10 01:27:36 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If we get an invalid address, return this so that comparisons with
|
|
|
|
* FDT_ADDR_T_NONE work correctly
|
|
|
|
*/
|
|
|
|
if (addr == 0xffffffff)
|
|
|
|
return addr;
|
|
|
|
else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
|
2015-11-30 05:17:53 +09:00
|
|
|
return addr & PCI_BASE_ADDRESS_IO_MASK;
|
|
|
|
else
|
|
|
|
return addr & PCI_BASE_ADDRESS_MEM_MASK;
|
|
|
|
}
|
|
|
|
|
2016-01-19 12:19:15 +09:00
|
|
|
void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
|
|
|
|
{
|
|
|
|
int bar;
|
|
|
|
|
|
|
|
bar = PCI_BASE_ADDRESS_0 + barnum * 4;
|
|
|
|
dm_pci_write_config32(dev, bar, addr);
|
|
|
|
}
|
|
|
|
|
2015-11-30 05:18:03 +09:00
|
|
|
static int _dm_pci_bus_to_phys(struct udevice *ctlr,
|
|
|
|
pci_addr_t bus_addr, unsigned long flags,
|
|
|
|
unsigned long skip_mask, phys_addr_t *pa)
|
|
|
|
{
|
|
|
|
struct pci_controller *hose = dev_get_uclass_priv(ctlr);
|
|
|
|
struct pci_region *res;
|
|
|
|
int i;
|
|
|
|
|
2018-06-10 22:25:06 +09:00
|
|
|
if (hose->region_count == 0) {
|
|
|
|
*pa = bus_addr;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-11-30 05:18:03 +09:00
|
|
|
for (i = 0; i < hose->region_count; i++) {
|
|
|
|
res = &hose->regions[i];
|
|
|
|
|
|
|
|
if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (res->flags & skip_mask)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (bus_addr >= res->bus_start &&
|
|
|
|
(bus_addr - res->bus_start) < res->size) {
|
|
|
|
*pa = (bus_addr - res->bus_start + res->phys_start);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
|
|
|
phys_addr_t phys_addr = 0;
|
|
|
|
struct udevice *ctlr;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* The root controller has the region information */
|
|
|
|
ctlr = pci_get_controller(dev);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* if PCI_REGION_MEM is set we do a two pass search with preference
|
|
|
|
* on matches that don't have PCI_REGION_SYS_MEMORY set
|
|
|
|
*/
|
|
|
|
if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
|
|
|
|
ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
|
|
|
|
flags, PCI_REGION_SYS_MEMORY,
|
|
|
|
&phys_addr);
|
|
|
|
if (!ret)
|
|
|
|
return phys_addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
puts("pci_hose_bus_to_phys: invalid physical address\n");
|
|
|
|
|
|
|
|
return phys_addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
|
|
|
|
unsigned long flags, unsigned long skip_mask,
|
|
|
|
pci_addr_t *ba)
|
|
|
|
{
|
|
|
|
struct pci_region *res;
|
|
|
|
struct udevice *ctlr;
|
|
|
|
pci_addr_t bus_addr;
|
|
|
|
int i;
|
|
|
|
struct pci_controller *hose;
|
|
|
|
|
|
|
|
/* The root controller has the region information */
|
|
|
|
ctlr = pci_get_controller(dev);
|
|
|
|
hose = dev_get_uclass_priv(ctlr);
|
|
|
|
|
2018-06-10 22:25:06 +09:00
|
|
|
if (hose->region_count == 0) {
|
|
|
|
*ba = phys_addr;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-11-30 05:18:03 +09:00
|
|
|
for (i = 0; i < hose->region_count; i++) {
|
|
|
|
res = &hose->regions[i];
|
|
|
|
|
|
|
|
if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (res->flags & skip_mask)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
bus_addr = phys_addr - res->phys_start + res->bus_start;
|
|
|
|
|
|
|
|
if (bus_addr >= res->bus_start &&
|
|
|
|
(bus_addr - res->bus_start) < res->size) {
|
|
|
|
*ba = bus_addr;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
|
|
|
|
unsigned long flags)
|
|
|
|
{
|
|
|
|
pci_addr_t bus_addr = 0;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* if PCI_REGION_MEM is set we do a two pass search with preference
|
|
|
|
* on matches that don't have PCI_REGION_SYS_MEMORY set
|
|
|
|
*/
|
|
|
|
if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
|
|
|
|
ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
|
|
|
|
PCI_REGION_SYS_MEMORY, &bus_addr);
|
|
|
|
if (!ret)
|
|
|
|
return bus_addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
|
|
|
|
|
|
|
|
if (ret)
|
|
|
|
puts("pci_hose_phys_to_bus: invalid physical address\n");
|
|
|
|
|
|
|
|
return bus_addr;
|
|
|
|
}
|
|
|
|
|
2019-06-07 17:24:23 +09:00
|
|
|
static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
|
|
|
|
int ea_off)
|
|
|
|
{
|
|
|
|
int ea_cnt, i, entry_size;
|
|
|
|
int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
|
|
|
|
u32 ea_entry;
|
|
|
|
phys_addr_t addr;
|
|
|
|
|
|
|
|
/* EA capability structure header */
|
|
|
|
dm_pci_read_config32(dev, ea_off, &ea_entry);
|
|
|
|
ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
|
|
|
|
ea_off += PCI_EA_FIRST_ENT;
|
|
|
|
|
|
|
|
for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
|
|
|
|
/* Entry header */
|
|
|
|
dm_pci_read_config32(dev, ea_off, &ea_entry);
|
|
|
|
entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
|
|
|
|
|
|
|
|
if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
/* Base address, 1st DW */
|
|
|
|
dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
|
|
|
|
addr = ea_entry & PCI_EA_FIELD_MASK;
|
|
|
|
if (ea_entry & PCI_EA_IS_64) {
|
|
|
|
/* Base address, 2nd DW, skip over 4B MaxOffset */
|
|
|
|
dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
|
|
|
|
addr |= ((u64)ea_entry) << 32;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* size ignored for now */
|
|
|
|
return map_physmem(addr, flags, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-11-30 05:18:03 +09:00
|
|
|
void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
|
|
|
|
{
|
|
|
|
pci_addr_t pci_bus_addr;
|
|
|
|
u32 bar_response;
|
2019-06-07 17:24:23 +09:00
|
|
|
int ea_off;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* if the function supports Enhanced Allocation use that instead of
|
|
|
|
* BARs
|
|
|
|
*/
|
|
|
|
ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
|
|
|
|
if (ea_off)
|
|
|
|
return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
|
2015-11-30 05:18:03 +09:00
|
|
|
|
|
|
|
/* read BAR address */
|
|
|
|
dm_pci_read_config32(dev, bar, &bar_response);
|
|
|
|
pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Pass "0" as the length argument to pci_bus_to_virt. The arg
|
|
|
|
* isn't actualy used on any platform because u-boot assumes a static
|
|
|
|
* linear mapping. In the future, this could read the BAR size
|
|
|
|
* and pass that as the size if needed.
|
|
|
|
*/
|
|
|
|
return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
|
|
|
|
}
|
|
|
|
|
2018-10-15 18:21:21 +09:00
|
|
|
static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
|
2018-08-03 17:14:52 +09:00
|
|
|
{
|
|
|
|
int ttl = PCI_FIND_CAP_TTL;
|
|
|
|
u8 id;
|
|
|
|
u16 ent;
|
|
|
|
|
|
|
|
dm_pci_read_config8(dev, pos, &pos);
|
2018-10-15 18:21:21 +09:00
|
|
|
|
2018-08-03 17:14:52 +09:00
|
|
|
while (ttl--) {
|
|
|
|
if (pos < PCI_STD_HEADER_SIZEOF)
|
|
|
|
break;
|
|
|
|
pos &= ~3;
|
|
|
|
dm_pci_read_config16(dev, pos, &ent);
|
|
|
|
|
|
|
|
id = ent & 0xff;
|
|
|
|
if (id == 0xff)
|
|
|
|
break;
|
|
|
|
if (id == cap)
|
|
|
|
return pos;
|
|
|
|
pos = (ent >> 8);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-10-15 18:21:21 +09:00
|
|
|
int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
|
|
|
|
{
|
|
|
|
return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
|
|
|
|
cap);
|
|
|
|
}
|
|
|
|
|
|
|
|
int dm_pci_find_capability(struct udevice *dev, int cap)
|
|
|
|
{
|
|
|
|
u16 status;
|
|
|
|
u8 header_type;
|
|
|
|
u8 pos;
|
|
|
|
|
|
|
|
dm_pci_read_config16(dev, PCI_STATUS, &status);
|
|
|
|
if (!(status & PCI_STATUS_CAP_LIST))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
|
|
|
|
if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
|
|
|
|
pos = PCI_CB_CAPABILITY_LIST;
|
|
|
|
else
|
|
|
|
pos = PCI_CAPABILITY_LIST;
|
|
|
|
|
|
|
|
return _dm_pci_find_next_capability(dev, pos, cap);
|
|
|
|
}
|
|
|
|
|
|
|
|
int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
|
2018-08-03 17:14:52 +09:00
|
|
|
{
|
|
|
|
u32 header;
|
|
|
|
int ttl;
|
|
|
|
int pos = PCI_CFG_SPACE_SIZE;
|
|
|
|
|
|
|
|
/* minimum 8 bytes per capability */
|
|
|
|
ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
|
|
|
|
|
2018-10-15 18:21:21 +09:00
|
|
|
if (start)
|
|
|
|
pos = start;
|
|
|
|
|
2018-08-03 17:14:52 +09:00
|
|
|
dm_pci_read_config32(dev, pos, &header);
|
|
|
|
/*
|
|
|
|
* If we have no capabilities, this is indicated by cap ID,
|
|
|
|
* cap version and next pointer all being 0.
|
|
|
|
*/
|
|
|
|
if (header == 0)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
while (ttl--) {
|
|
|
|
if (PCI_EXT_CAP_ID(header) == cap)
|
|
|
|
return pos;
|
|
|
|
|
|
|
|
pos = PCI_EXT_CAP_NEXT(header);
|
|
|
|
if (pos < PCI_CFG_SPACE_SIZE)
|
|
|
|
break;
|
|
|
|
|
|
|
|
dm_pci_read_config32(dev, pos, &header);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-10-15 18:21:21 +09:00
|
|
|
int dm_pci_find_ext_capability(struct udevice *dev, int cap)
|
|
|
|
{
|
|
|
|
return dm_pci_find_next_ext_capability(dev, 0, cap);
|
|
|
|
}
|
|
|
|
|
2019-06-07 17:24:25 +09:00
|
|
|
int dm_pci_flr(struct udevice *dev)
|
|
|
|
{
|
|
|
|
int pcie_off;
|
|
|
|
u32 cap;
|
|
|
|
|
|
|
|
/* look for PCI Express Capability */
|
|
|
|
pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
|
|
|
|
if (!pcie_off)
|
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
/* check FLR capability */
|
|
|
|
dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
|
|
|
|
if (!(cap & PCI_EXP_DEVCAP_FLR))
|
|
|
|
return -ENOENT;
|
|
|
|
|
|
|
|
dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
|
|
|
|
PCI_EXP_DEVCTL_BCR_FLR);
|
|
|
|
|
|
|
|
/* wait 100ms, per PCI spec */
|
|
|
|
mdelay(100);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-03-06 04:25:25 +09:00
|
|
|
UCLASS_DRIVER(pci) = {
|
|
|
|
.id = UCLASS_PCI,
|
|
|
|
.name = "pci",
|
2015-05-11 12:08:06 +09:00
|
|
|
.flags = DM_UC_FLAG_SEQ_ALIAS,
|
2016-07-06 08:10:10 +09:00
|
|
|
.post_bind = dm_scan_fdt_dev,
|
2015-03-06 04:25:25 +09:00
|
|
|
.pre_probe = pci_uclass_pre_probe,
|
|
|
|
.post_probe = pci_uclass_post_probe,
|
|
|
|
.child_post_bind = pci_uclass_child_post_bind,
|
|
|
|
.per_device_auto_alloc_size = sizeof(struct pci_controller),
|
|
|
|
.per_child_platdata_auto_alloc_size =
|
|
|
|
sizeof(struct pci_child_platdata),
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct dm_pci_ops pci_bridge_ops = {
|
|
|
|
.read_config = pci_bridge_read_config,
|
|
|
|
.write_config = pci_bridge_write_config,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct udevice_id pci_bridge_ids[] = {
|
|
|
|
{ .compatible = "pci-bridge" },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(pci_bridge_drv) = {
|
|
|
|
.name = "pci_bridge_drv",
|
|
|
|
.id = UCLASS_PCI,
|
|
|
|
.of_match = pci_bridge_ids,
|
|
|
|
.ops = &pci_bridge_ops,
|
|
|
|
};
|
|
|
|
|
|
|
|
UCLASS_DRIVER(pci_generic) = {
|
|
|
|
.id = UCLASS_PCI_GENERIC,
|
|
|
|
.name = "pci_generic",
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct udevice_id pci_generic_ids[] = {
|
|
|
|
{ .compatible = "pci-generic" },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(pci_generic_drv) = {
|
|
|
|
.name = "pci_generic_drv",
|
|
|
|
.id = UCLASS_PCI_GENERIC,
|
|
|
|
.of_match = pci_generic_ids,
|
|
|
|
};
|
Implement "pci enum" command for CONFIG_DM_PCI
With CONFIG_DM_PCI enabled, PCI buses are not enumerated at boot, as they
are without that config option enabled. No command exists to enumerate the
PCI buses. Hence, unless some board-specific code causes PCI enumeration,
PCI-based Ethernet devices are not detected, and network access is not
available.
This patch implements "pci enum" in the CONFIG_DM_PCI case, thus giving a
mechanism whereby PCI can be enumerated.
do_pci()'s handling of case 'e' is moved into a single location before the
dev variable is assigned, in order to skip calculation of dev. The enum
sub-command doesn't need the dev value, and skipping its calculation
avoids an irrelevant error being printed.
Using a command to initialize PCI like this has a disadvantage relative to
enumerating PCI at boot. In particular, Ethernet devices are not probed
during PCI enumeration, but only when used. This defers setting variables
such as ethact, ethaddr, etc. until the first network-related command is
executed. Hopefully this will not cause further issues. Perhaps in the
long term, we need a "net start/enum" command too?
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-27 03:10:11 +09:00
|
|
|
|
|
|
|
void pci_init(void)
|
|
|
|
{
|
|
|
|
struct udevice *bus;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enumerate all known controller devices. Enumeration has the side-
|
|
|
|
* effect of probing them, so PCIe devices will be enumerated too.
|
|
|
|
*/
|
2019-05-21 19:04:31 +09:00
|
|
|
for (uclass_first_device_check(UCLASS_PCI, &bus);
|
Implement "pci enum" command for CONFIG_DM_PCI
With CONFIG_DM_PCI enabled, PCI buses are not enumerated at boot, as they
are without that config option enabled. No command exists to enumerate the
PCI buses. Hence, unless some board-specific code causes PCI enumeration,
PCI-based Ethernet devices are not detected, and network access is not
available.
This patch implements "pci enum" in the CONFIG_DM_PCI case, thus giving a
mechanism whereby PCI can be enumerated.
do_pci()'s handling of case 'e' is moved into a single location before the
dev variable is assigned, in order to skip calculation of dev. The enum
sub-command doesn't need the dev value, and skipping its calculation
avoids an irrelevant error being printed.
Using a command to initialize PCI like this has a disadvantage relative to
enumerating PCI at boot. In particular, Ethernet devices are not probed
during PCI enumeration, but only when used. This defers setting variables
such as ethact, ethaddr, etc. until the first network-related command is
executed. Hopefully this will not cause further issues. Perhaps in the
long term, we need a "net start/enum" command too?
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-27 03:10:11 +09:00
|
|
|
bus;
|
2019-05-21 19:04:31 +09:00
|
|
|
uclass_next_device_check(&bus)) {
|
Implement "pci enum" command for CONFIG_DM_PCI
With CONFIG_DM_PCI enabled, PCI buses are not enumerated at boot, as they
are without that config option enabled. No command exists to enumerate the
PCI buses. Hence, unless some board-specific code causes PCI enumeration,
PCI-based Ethernet devices are not detected, and network access is not
available.
This patch implements "pci enum" in the CONFIG_DM_PCI case, thus giving a
mechanism whereby PCI can be enumerated.
do_pci()'s handling of case 'e' is moved into a single location before the
dev variable is assigned, in order to skip calculation of dev. The enum
sub-command doesn't need the dev value, and skipping its calculation
avoids an irrelevant error being printed.
Using a command to initialize PCI like this has a disadvantage relative to
enumerating PCI at boot. In particular, Ethernet devices are not probed
during PCI enumeration, but only when used. This defers setting variables
such as ethact, ethaddr, etc. until the first network-related command is
executed. Hopefully this will not cause further issues. Perhaps in the
long term, we need a "net start/enum" command too?
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-27 03:10:11 +09:00
|
|
|
;
|
|
|
|
}
|
|
|
|
}
|