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dm: pci: Support decoding ranges with duplicate entries

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At present we add a new resource entry for every range entry. But some range
entries refer to configuration regions. To make this work, avoid adding two
regions of the same type. The later ranges will overwrite the earlier
(configuration) ones.

There does not seem to be a way to distinguish the configuration ranges
other than by ordering (as per the device tree binding).

We could perhaps instead just store one region of each type in a simple
array. Once we are sure that we don't need to support multiple regions, we
could change this. It would be easier to do it when all drivers are
converted to use driver model for PCI.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Simon Glass 2015-11-19 20:26:58 -07:00
parent 2084c5af6d
commit 9526d83ac5
1 changed files with 10 additions and 3 deletions
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13
drivers/pci/pci-uclass.c
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@ -704,6 +704,7 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
int space_code;
u32 flags;
int type;
int pos;
if (len < cells_per_record)
break;
@ -726,9 +727,15 @@ static int decode_regions(struct pci_controller *hose, const void *blob,
} else {
continue;
}
debug(" - type=%d\n", type);
pci_set_region(hose->regions + hose->region_count++, pci_addr,
addr, size, type);
pos = -1;
for (i = 0; i < hose->region_count; i++) {
if (hose->regions[i].flags == type)
pos = i;
}
if (pos == -1)
pos = hose->region_count++;
debug(" - type=%d, pos=%d\n", type, pos);
pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
}
/* Add a region for our local memory */