u-boot-brain/arch/arm/mach-k3/lowlevel_init.S

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
 *	Lokesh Vutla <lokeshvutla@ti.com>
 */

#include <linux/linkage.h>

ENTRY(lowlevel_init)

	mrc	p15, 0, r0, c0, c0, 5		@ Read MPIDR
	and	r0, #0xff
	cmp	r0, #0x0
	bne	park_cpu
	bx	lr
park_cpu:
	wfi
	b	park_cpu

ENDPROC(lowlevel_init)
armv7r: K3: Allow SPL to run only on core 0 Based on the MCU R5 efuse settings, R5F cores in MCU domain either work in split mode or in lock step mode. If efuse settings are in lockstep mode: ROM release R5 cores and SPL continues to run on the R5 core is lockstep mode. If efuse settings are in split mode: ROM releases both the R5 cores simultaneously and allow SPL to run on both the cores. In this case it is bootloader's responsibility to detect core 1 and park it. Else both the core will be running bootloader independently which might result in an unexpected behaviour. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> 2018-11-15 14:34:50 +09:00			`/* SPDX-License-Identifier: GPL-2.0+ */`
			`/*`
			`* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/`
			`* Lokesh Vutla <lokeshvutla@ti.com>`
			`*/`

			`#include <linux/linkage.h>`

			`ENTRY(lowlevel_init)`

			`mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR`
			`and r0, #0xff`
			`cmp r0, #0x0`
			`bne park_cpu`
			`bx lr`
			`park_cpu:`
			`wfi`
			`b park_cpu`

			`ENDPROC(lowlevel_init)`