2014-12-17 16:50:44 +09:00
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _X86_ARCH_TNC_H_
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#define _X86_ARCH_TNC_H_
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2015-10-01 16:36:04 +09:00
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/* IGD Control Register */
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#define IGD_GC 0x50
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#define VGA_DISABLE 0x00020000
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#define GMS_MASK 0x00700000
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2015-04-24 19:10:06 +09:00
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/* Memory BAR Enable */
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#define MEM_BAR_EN 0x00000001
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2014-12-17 16:50:44 +09:00
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2015-04-24 19:10:06 +09:00
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/* LPC PCI Configuration Registers */
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#define LPC_RCBA 0xf0
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/* Root Complex Register Block */
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struct tnc_rcba {
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u32 rctl;
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u32 esd;
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u32 rsvd1[2];
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u32 hdd;
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u32 rsvd2;
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u32 hdba;
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u32 rsvd3[3129];
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u32 d31ip;
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u32 rsvd4[3];
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u32 d27ip;
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u32 rsvd5;
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u32 d02ip;
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u32 rsvd6;
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u32 d26ip;
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u32 d25ip;
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u32 d24ip;
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u32 d23ip;
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u32 d03ip;
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u32 rsvd7[3];
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u16 d31ir;
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u16 rsvd8[3];
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u16 d27ir;
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u16 d26ir;
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u16 d25ir;
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u16 d24ir;
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u16 d23ir;
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u16 rsvd9[7];
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u16 d02ir;
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u16 d03ir;
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};
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2014-12-17 16:50:44 +09:00
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#endif /* _X86_ARCH_TNC_H_ */
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