2014-12-17 16:50:36 +09:00
|
|
|
/*
|
|
|
|
* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
|
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
|
|
|
#include <asm/io.h>
|
2015-05-25 23:35:04 +09:00
|
|
|
#include <asm/irq.h>
|
2014-12-17 16:50:44 +09:00
|
|
|
#include <asm/pci.h>
|
2014-12-17 16:50:36 +09:00
|
|
|
#include <asm/post.h>
|
2015-04-24 19:10:06 +09:00
|
|
|
#include <asm/arch/device.h>
|
2015-05-25 23:35:04 +09:00
|
|
|
#include <asm/arch/tnc.h>
|
2015-01-28 14:13:36 +09:00
|
|
|
#include <asm/fsp/fsp_support.h>
|
2014-12-17 16:50:36 +09:00
|
|
|
#include <asm/processor.h>
|
|
|
|
|
2014-12-17 16:50:44 +09:00
|
|
|
static void unprotect_spi_flash(void)
|
|
|
|
{
|
|
|
|
u32 bc;
|
|
|
|
|
2015-04-13 20:03:42 +09:00
|
|
|
bc = x86_pci_read_config32(TNC_LPC, 0xd8);
|
2014-12-17 16:50:44 +09:00
|
|
|
bc |= 0x1; /* unprotect the flash */
|
2015-04-13 20:03:42 +09:00
|
|
|
x86_pci_write_config32(TNC_LPC, 0xd8, bc);
|
2014-12-17 16:50:44 +09:00
|
|
|
}
|
|
|
|
|
2015-10-01 16:36:04 +09:00
|
|
|
static void __maybe_unused disable_igd(void)
|
|
|
|
{
|
|
|
|
u32 gc;
|
|
|
|
|
|
|
|
gc = x86_pci_read_config32(TNC_IGD, IGD_GC);
|
|
|
|
gc &= ~GMS_MASK;
|
|
|
|
gc |= VGA_DISABLE;
|
|
|
|
x86_pci_write_config32(TNC_IGD, IGD_GC, gc);
|
|
|
|
}
|
|
|
|
|
2014-12-17 16:50:36 +09:00
|
|
|
int arch_cpu_init(void)
|
|
|
|
{
|
2014-12-17 16:50:44 +09:00
|
|
|
int ret;
|
|
|
|
|
2014-12-17 16:50:36 +09:00
|
|
|
post_code(POST_CPU_INIT);
|
|
|
|
#ifdef CONFIG_SYS_X86_TSC_TIMER
|
|
|
|
timer_set_base(rdtsc());
|
|
|
|
#endif
|
|
|
|
|
2014-12-17 16:50:44 +09:00
|
|
|
ret = x86_cpu_init_f();
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
return 0;
|
2014-12-17 16:50:36 +09:00
|
|
|
}
|
2015-04-24 19:10:06 +09:00
|
|
|
|
2015-10-01 16:36:04 +09:00
|
|
|
int arch_early_init_r(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_DISABLE_IGD
|
|
|
|
disable_igd();
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2015-05-25 23:35:04 +09:00
|
|
|
void cpu_irq_init(void)
|
|
|
|
{
|
|
|
|
struct tnc_rcba *rcba;
|
|
|
|
u32 base;
|
|
|
|
|
|
|
|
base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
|
|
|
|
base &= ~MEM_BAR_EN;
|
|
|
|
rcba = (struct tnc_rcba *)base;
|
|
|
|
|
|
|
|
/* Make sure all internal PCI devices are using INTA */
|
|
|
|
writel(INTA, &rcba->d02ip);
|
|
|
|
writel(INTA, &rcba->d03ip);
|
|
|
|
writel(INTA, &rcba->d27ip);
|
|
|
|
writel(INTA, &rcba->d31ip);
|
|
|
|
writel(INTA, &rcba->d23ip);
|
|
|
|
writel(INTA, &rcba->d24ip);
|
|
|
|
writel(INTA, &rcba->d25ip);
|
|
|
|
writel(INTA, &rcba->d26ip);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Route TunnelCreek PCI device interrupt pin to PIRQ
|
|
|
|
*
|
|
|
|
* Since PCIe downstream ports received INTx are routed to PIRQ
|
2015-06-23 13:18:55 +09:00
|
|
|
* A/B/C/D directly and not configurable, we have to route PCIe
|
|
|
|
* root ports' INTx to PIRQ A/B/C/D as well. For other devices
|
|
|
|
* on TunneCreek, route them to PIRQ E/F/G/H.
|
2015-05-25 23:35:04 +09:00
|
|
|
*/
|
|
|
|
writew(PIRQE, &rcba->d02ir);
|
|
|
|
writew(PIRQF, &rcba->d03ir);
|
|
|
|
writew(PIRQG, &rcba->d27ir);
|
|
|
|
writew(PIRQH, &rcba->d31ir);
|
2015-06-23 13:18:55 +09:00
|
|
|
writew(PIRQA, &rcba->d23ir);
|
|
|
|
writew(PIRQB, &rcba->d24ir);
|
|
|
|
writew(PIRQC, &rcba->d25ir);
|
|
|
|
writew(PIRQD, &rcba->d26ir);
|
2015-05-25 23:35:04 +09:00
|
|
|
}
|
|
|
|
|
2015-04-24 19:10:06 +09:00
|
|
|
int arch_misc_init(void)
|
|
|
|
{
|
2015-08-20 22:40:21 +09:00
|
|
|
unprotect_spi_flash();
|
|
|
|
|
2015-08-10 22:05:08 +09:00
|
|
|
return pirq_init();
|
2015-04-24 19:10:06 +09:00
|
|
|
}
|