2018-05-07 06:58:06 +09:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2008-10-31 06:47:16 +09:00
|
|
|
/*
|
2011-01-07 14:42:19 +09:00
|
|
|
* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
|
2020-05-19 12:06:43 +09:00
|
|
|
* Copyright 2019-2020 NXP
|
2008-10-31 06:47:16 +09:00
|
|
|
* Andy Fleming
|
|
|
|
*
|
|
|
|
* Based vaguely on the pxa mmc code:
|
|
|
|
* (C) Copyright 2003
|
|
|
|
* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <config.h>
|
|
|
|
#include <common.h>
|
|
|
|
#include <command.h>
|
2019-11-15 04:57:39 +09:00
|
|
|
#include <cpu_func.h>
|
2016-07-19 16:33:36 +09:00
|
|
|
#include <errno.h>
|
2009-06-10 05:25:29 +09:00
|
|
|
#include <hwconfig.h>
|
2008-10-31 06:47:16 +09:00
|
|
|
#include <mmc.h>
|
|
|
|
#include <part.h>
|
|
|
|
#include <malloc.h>
|
|
|
|
#include <fsl_esdhc.h>
|
2009-06-10 05:25:29 +09:00
|
|
|
#include <fdt_support.h>
|
2020-05-11 02:39:56 +09:00
|
|
|
#include <asm/cache.h>
|
2020-10-31 12:38:53 +09:00
|
|
|
#include <asm/global_data.h>
|
2008-10-31 06:47:16 +09:00
|
|
|
#include <asm/io.h>
|
2016-03-25 15:16:56 +09:00
|
|
|
#include <dm.h>
|
2020-02-03 23:36:16 +09:00
|
|
|
#include <dm/device_compat.h>
|
2020-05-11 02:40:13 +09:00
|
|
|
#include <linux/bitops.h>
|
2020-05-11 02:40:11 +09:00
|
|
|
#include <linux/delay.h>
|
2020-09-23 19:42:48 +09:00
|
|
|
#include <linux/dma-mapping.h>
|
2020-10-12 17:07:14 +09:00
|
|
|
#include <sdhci.h>
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
|
|
|
|
struct fsl_esdhc {
|
2013-10-30 12:37:55 +09:00
|
|
|
uint dsaddr; /* SDMA system address register */
|
|
|
|
uint blkattr; /* Block attributes register */
|
|
|
|
uint cmdarg; /* Command argument register */
|
|
|
|
uint xfertyp; /* Transfer type register */
|
|
|
|
uint cmdrsp0; /* Command response 0 register */
|
|
|
|
uint cmdrsp1; /* Command response 1 register */
|
|
|
|
uint cmdrsp2; /* Command response 2 register */
|
|
|
|
uint cmdrsp3; /* Command response 3 register */
|
|
|
|
uint datport; /* Buffer data port register */
|
|
|
|
uint prsstat; /* Present state register */
|
|
|
|
uint proctl; /* Protocol control register */
|
|
|
|
uint sysctl; /* System Control Register */
|
|
|
|
uint irqstat; /* Interrupt status register */
|
|
|
|
uint irqstaten; /* Interrupt status enable register */
|
|
|
|
uint irqsigen; /* Interrupt signal enable register */
|
|
|
|
uint autoc12err; /* Auto CMD error status register */
|
|
|
|
uint hostcapblt; /* Host controller capabilities register */
|
|
|
|
uint wml; /* Watermark level register */
|
2019-06-21 12:42:29 +09:00
|
|
|
char reserved1[8]; /* reserved */
|
2013-10-30 12:37:55 +09:00
|
|
|
uint fevt; /* Force event register */
|
|
|
|
uint admaes; /* ADMA error status register */
|
2020-10-12 17:07:14 +09:00
|
|
|
uint adsaddrl; /* ADMA system address low register */
|
|
|
|
uint adsaddrh; /* ADMA system address high register */
|
|
|
|
char reserved2[156];
|
2013-10-30 12:37:55 +09:00
|
|
|
uint hostver; /* Host controller version register */
|
2019-06-21 12:42:29 +09:00
|
|
|
char reserved3[4]; /* reserved */
|
2018-01-21 20:00:22 +09:00
|
|
|
uint dmaerraddr; /* DMA error address register */
|
2019-06-21 12:42:29 +09:00
|
|
|
char reserved4[4]; /* reserved */
|
2018-01-21 20:00:22 +09:00
|
|
|
uint dmaerrattr; /* DMA error attribute register */
|
2019-06-21 12:42:29 +09:00
|
|
|
char reserved5[4]; /* reserved */
|
2013-10-30 12:37:55 +09:00
|
|
|
uint hostcapblt2; /* Host controller capabilities register 2 */
|
2020-09-01 17:58:01 +09:00
|
|
|
char reserved6[8]; /* reserved */
|
|
|
|
uint tbctl; /* Tuning block control register */
|
2020-09-01 17:58:05 +09:00
|
|
|
char reserved7[32]; /* reserved */
|
|
|
|
uint sdclkctl; /* SD clock control register */
|
|
|
|
uint sdtimingctl; /* SD timing control register */
|
|
|
|
char reserved8[20]; /* reserved */
|
|
|
|
uint dllcfg0; /* DLL config 0 register */
|
2021-03-17 23:01:37 +09:00
|
|
|
uint dllcfg1; /* DLL config 1 register */
|
|
|
|
char reserved9[8]; /* reserved */
|
2020-10-20 12:04:52 +09:00
|
|
|
uint dllstat0; /* DLL status 0 register */
|
|
|
|
char reserved10[664];/* reserved */
|
2019-06-21 12:42:29 +09:00
|
|
|
uint esdhcctl; /* eSDHC control register */
|
2008-10-31 06:47:16 +09:00
|
|
|
};
|
|
|
|
|
2017-07-30 02:35:21 +09:00
|
|
|
struct fsl_esdhc_plat {
|
|
|
|
struct mmc_config cfg;
|
|
|
|
struct mmc mmc;
|
|
|
|
};
|
|
|
|
|
2016-03-25 15:16:56 +09:00
|
|
|
/**
|
|
|
|
* struct fsl_esdhc_priv
|
|
|
|
*
|
|
|
|
* @esdhc_regs: registers of the sdhc controller
|
|
|
|
* @sdhc_clk: Current clk of the sdhc controller
|
|
|
|
* @bus_width: bus width, 1bit, 4bit or 8bit
|
|
|
|
* @cfg: mmc config
|
|
|
|
* @mmc: mmc
|
|
|
|
* Following is used when Driver Model is enabled for MMC
|
|
|
|
* @dev: pointer for the device
|
|
|
|
* @cd_gpio: gpio for card detection
|
mmc: fsl: introduce wp_enable
Introudce wp_enable. To check WPSPL, wp_enable needs to be set
to 1 in board code.
Take i.MX6UL for example, for some boards, they do not use WP singal,
so they does not configure USDHC1_WP_SELECT_INPUT, and its default
value is 0(GPIO1_IO02). However GPIO1_IO02 is muxed for i2c usage and
SION bit set. So USDHC controller can always get wp signal and WPSPL
shows write protect and blocks driver continuing. This is not what
we want to see, so add wp_enable, and if set to 0, just omit the
WPSPL checking and this does not effect normal working of usdhc
controller.
If wp-gpios is provided in dts, wp_enable is set to 1, otherwise 0.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-15 11:53:02 +09:00
|
|
|
* @wp_gpio: gpio for write protection
|
2016-03-25 15:16:56 +09:00
|
|
|
*/
|
|
|
|
struct fsl_esdhc_priv {
|
|
|
|
struct fsl_esdhc *esdhc_regs;
|
|
|
|
unsigned int sdhc_clk;
|
2019-12-19 19:59:30 +09:00
|
|
|
bool is_sdhc_per_clk;
|
2018-01-21 20:00:24 +09:00
|
|
|
unsigned int clock;
|
2019-10-21 19:09:07 +09:00
|
|
|
#if !CONFIG_IS_ENABLED(DM_MMC)
|
2016-03-25 15:16:56 +09:00
|
|
|
struct mmc *mmc;
|
2017-07-30 02:35:24 +09:00
|
|
|
#endif
|
2016-03-25 15:16:56 +09:00
|
|
|
struct udevice *dev;
|
2020-10-12 17:07:14 +09:00
|
|
|
struct sdhci_adma_desc *adma_desc_table;
|
2020-09-23 19:42:48 +09:00
|
|
|
dma_addr_t dma_addr;
|
2016-03-25 15:16:56 +09:00
|
|
|
};
|
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
/* Return the XFERTYP flags for a given command and data packet */
|
2012-10-29 22:34:44 +09:00
|
|
|
static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
|
2008-10-31 06:47:16 +09:00
|
|
|
{
|
|
|
|
uint xfertyp = 0;
|
|
|
|
|
|
|
|
if (data) {
|
2009-10-05 19:11:58 +09:00
|
|
|
xfertyp |= XFERTYP_DPSEL;
|
2020-10-12 17:07:13 +09:00
|
|
|
if (!IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO) &&
|
|
|
|
cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
|
2020-09-01 17:58:01 +09:00
|
|
|
cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
|
|
|
|
xfertyp |= XFERTYP_DMAEN;
|
2008-10-31 06:47:16 +09:00
|
|
|
if (data->blocks > 1) {
|
|
|
|
xfertyp |= XFERTYP_MSBSEL;
|
|
|
|
xfertyp |= XFERTYP_BCEN;
|
2020-10-12 17:07:13 +09:00
|
|
|
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111))
|
|
|
|
xfertyp |= XFERTYP_AC12EN;
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_READ)
|
|
|
|
xfertyp |= XFERTYP_DTDSEL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cmd->resp_type & MMC_RSP_CRC)
|
|
|
|
xfertyp |= XFERTYP_CCCEN;
|
|
|
|
if (cmd->resp_type & MMC_RSP_OPCODE)
|
|
|
|
xfertyp |= XFERTYP_CICEN;
|
|
|
|
if (cmd->resp_type & MMC_RSP_136)
|
|
|
|
xfertyp |= XFERTYP_RSPTYP_136;
|
|
|
|
else if (cmd->resp_type & MMC_RSP_BUSY)
|
|
|
|
xfertyp |= XFERTYP_RSPTYP_48_BUSY;
|
|
|
|
else if (cmd->resp_type & MMC_RSP_PRESENT)
|
|
|
|
xfertyp |= XFERTYP_RSPTYP_48;
|
|
|
|
|
fsl_esdhc: Fix multi-block read restriction on i.MX53 eSDHCv2
For freescale i.MX53 eSDHCv2, when using CMD12, cmdtype need
to be set to ABORT, otherwise, next read command will hang.
This is a software Software Restrictions in i.MX53 reference manual:
29.7.8 Multi-block Read
For pre-defined multi-block read operation, that is,the number of blocks
to read has been defined by previous CMD23 for MMC, or pre-defined number
of blocks in CMD53 for SDIO/SDCombo,or whatever multi-block read without
abort command at card side, an abort command, either automatic or manual
CMD12/CMD52, is still required by ESDHC after the pre-defined number of
blocks are done, to drive the internal state machine to idle mode. In this
case, the card may not respond to this extra abort command and ESDHC will
get Response Timeout. It is recommended to manually send an abort command
with RSPTYP[1:0] both bits cleared.
Signed-off-by: Jason Liu <jason.hui@linaro.org>
2011-03-22 10:32:31 +09:00
|
|
|
if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
|
|
|
|
xfertyp |= XFERTYP_CMDTYP_ABORT;
|
2016-01-21 18:33:19 +09:00
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
|
|
|
|
}
|
|
|
|
|
2009-10-05 19:11:58 +09:00
|
|
|
/*
|
|
|
|
* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
|
|
|
|
*/
|
2017-07-30 02:35:17 +09:00
|
|
|
static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
|
|
|
|
struct mmc_data *data)
|
2009-10-05 19:11:58 +09:00
|
|
|
{
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2009-10-05 19:11:58 +09:00
|
|
|
uint blocks;
|
|
|
|
char *buffer;
|
|
|
|
uint databuf;
|
|
|
|
uint size;
|
|
|
|
uint irqstat;
|
2017-10-30 06:08:58 +09:00
|
|
|
ulong start;
|
2009-10-05 19:11:58 +09:00
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_READ) {
|
|
|
|
blocks = data->blocks;
|
|
|
|
buffer = data->dest;
|
|
|
|
while (blocks) {
|
2017-10-30 06:08:58 +09:00
|
|
|
start = get_timer(0);
|
2009-10-05 19:11:58 +09:00
|
|
|
size = data->blocksize;
|
|
|
|
irqstat = esdhc_read32(®s->irqstat);
|
2017-10-30 06:08:58 +09:00
|
|
|
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) {
|
|
|
|
if (get_timer(start) > PIO_TIMEOUT) {
|
|
|
|
printf("\nData Read Failed in PIO Mode.");
|
|
|
|
return;
|
|
|
|
}
|
2009-10-05 19:11:58 +09:00
|
|
|
}
|
|
|
|
while (size && (!(irqstat & IRQSTAT_TC))) {
|
|
|
|
udelay(100); /* Wait before last byte transfer complete */
|
|
|
|
irqstat = esdhc_read32(®s->irqstat);
|
|
|
|
databuf = in_le32(®s->datport);
|
|
|
|
*((uint *)buffer) = databuf;
|
|
|
|
buffer += 4;
|
|
|
|
size -= 4;
|
|
|
|
}
|
|
|
|
blocks--;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
blocks = data->blocks;
|
2010-05-10 06:52:59 +09:00
|
|
|
buffer = (char *)data->src;
|
2009-10-05 19:11:58 +09:00
|
|
|
while (blocks) {
|
2017-10-30 06:08:58 +09:00
|
|
|
start = get_timer(0);
|
2009-10-05 19:11:58 +09:00
|
|
|
size = data->blocksize;
|
|
|
|
irqstat = esdhc_read32(®s->irqstat);
|
2017-10-30 06:08:58 +09:00
|
|
|
while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) {
|
|
|
|
if (get_timer(start) > PIO_TIMEOUT) {
|
|
|
|
printf("\nData Write Failed in PIO Mode.");
|
|
|
|
return;
|
|
|
|
}
|
2009-10-05 19:11:58 +09:00
|
|
|
}
|
|
|
|
while (size && (!(irqstat & IRQSTAT_TC))) {
|
|
|
|
udelay(100); /* Wait before last byte transfer complete */
|
|
|
|
databuf = *((uint *)buffer);
|
|
|
|
buffer += 4;
|
|
|
|
size -= 4;
|
|
|
|
irqstat = esdhc_read32(®s->irqstat);
|
|
|
|
out_le32(®s->datport, databuf);
|
|
|
|
}
|
|
|
|
blocks--;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-09-23 19:42:49 +09:00
|
|
|
static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv,
|
|
|
|
struct mmc_data *data)
|
2008-10-31 06:47:16 +09:00
|
|
|
{
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2020-09-23 19:42:49 +09:00
|
|
|
uint wml_value = data->blocksize / 4;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_READ) {
|
2011-02-09 12:54:10 +09:00
|
|
|
if (wml_value > WML_RD_WML_MAX)
|
|
|
|
wml_value = WML_RD_WML_MAX_VAL;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2010-02-09 19:23:33 +09:00
|
|
|
esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value);
|
2008-10-31 06:47:16 +09:00
|
|
|
} else {
|
2011-02-09 12:54:10 +09:00
|
|
|
if (wml_value > WML_WR_WML_MAX)
|
|
|
|
wml_value = WML_WR_WML_MAX_VAL;
|
2019-10-31 19:54:25 +09:00
|
|
|
|
2010-02-09 19:23:33 +09:00
|
|
|
esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK,
|
2020-09-23 19:42:49 +09:00
|
|
|
wml_value << 16);
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
2020-09-23 19:42:49 +09:00
|
|
|
}
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2020-09-23 19:42:49 +09:00
|
|
|
static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data)
|
|
|
|
{
|
|
|
|
uint trans_bytes = data->blocksize * data->blocks;
|
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2020-10-12 17:07:14 +09:00
|
|
|
phys_addr_t adma_addr;
|
2020-09-23 19:42:49 +09:00
|
|
|
void *buf;
|
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_WRITE)
|
|
|
|
buf = (void *)data->src;
|
|
|
|
else
|
|
|
|
buf = data->dest;
|
|
|
|
|
|
|
|
priv->dma_addr = dma_map_single(buf, trans_bytes,
|
|
|
|
mmc_get_dma_dir(data));
|
2020-10-12 17:07:14 +09:00
|
|
|
|
|
|
|
if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2) &&
|
|
|
|
priv->adma_desc_table) {
|
|
|
|
debug("Using ADMA2\n");
|
|
|
|
/* prefer ADMA2 if it is available */
|
|
|
|
sdhci_prepare_adma_table(priv->adma_desc_table, data,
|
|
|
|
priv->dma_addr);
|
|
|
|
|
|
|
|
adma_addr = virt_to_phys(priv->adma_desc_table);
|
|
|
|
esdhc_write32(®s->adsaddrl, lower_32_bits(adma_addr));
|
|
|
|
if (IS_ENABLED(CONFIG_DMA_ADDR_T_64BIT))
|
|
|
|
esdhc_write32(®s->adsaddrh, upper_32_bits(adma_addr));
|
|
|
|
esdhc_clrsetbits32(®s->proctl, PROCTL_DMAS_MASK,
|
|
|
|
PROCTL_DMAS_ADMA2);
|
|
|
|
} else {
|
|
|
|
debug("Using SDMA\n");
|
|
|
|
if (upper_32_bits(priv->dma_addr))
|
|
|
|
printf("Cannot use 64 bit addresses with SDMA\n");
|
|
|
|
esdhc_write32(®s->dsaddr, lower_32_bits(priv->dma_addr));
|
|
|
|
esdhc_clrsetbits32(®s->proctl, PROCTL_DMAS_MASK,
|
|
|
|
PROCTL_DMAS_SDMA);
|
|
|
|
}
|
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize);
|
2020-09-23 19:42:49 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
|
|
|
|
struct mmc_data *data)
|
|
|
|
{
|
|
|
|
int timeout;
|
|
|
|
bool is_write = data->flags & MMC_DATA_WRITE;
|
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
|
|
|
|
|
if (is_write && !(esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL)) {
|
|
|
|
printf("Can not write to locked SD card.\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2020-10-12 17:07:13 +09:00
|
|
|
if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO))
|
|
|
|
esdhc_setup_watermark_level(priv, data);
|
|
|
|
else
|
|
|
|
esdhc_setup_dma(priv, data);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
/* Calculate the timeout period for data transactions */
|
2011-03-03 12:48:56 +09:00
|
|
|
/*
|
|
|
|
* 1)Timeout period = (2^(timeout+13)) SD Clock cycles
|
|
|
|
* 2)Timeout period should be minimum 0.250sec as per SD Card spec
|
|
|
|
* So, Number of SD Clock cycles for 0.25sec should be minimum
|
|
|
|
* (SD Clock/sec * 0.25 sec) SD Clock cycles
|
mmc: fsl_esdhc: fix calculation of timeout for data transactions
Calculation of the timeout value should be based on actual clock value,
written to controller registers. Since mmc->tran_speed is either the
maximum allowed speed, or the preliminary value, that is be not yet
set to registers, the actual timeout, taken by the controller, based
on its clock settings, may be much longer than expected, based on
mmc->tran_speed value. In particular it happens at early initialization
stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while
actual clock setting, configured in the controller, is 400kHz.
It's more correct to use mmc->clock value for timeout calculation instead.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 16:40:41 +09:00
|
|
|
* = (mmc->clock * 1/4) SD Clock cycles
|
2011-03-03 12:48:56 +09:00
|
|
|
* As 1) >= 2)
|
mmc: fsl_esdhc: fix calculation of timeout for data transactions
Calculation of the timeout value should be based on actual clock value,
written to controller registers. Since mmc->tran_speed is either the
maximum allowed speed, or the preliminary value, that is be not yet
set to registers, the actual timeout, taken by the controller, based
on its clock settings, may be much longer than expected, based on
mmc->tran_speed value. In particular it happens at early initialization
stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while
actual clock setting, configured in the controller, is 400kHz.
It's more correct to use mmc->clock value for timeout calculation instead.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 16:40:41 +09:00
|
|
|
* => (2^(timeout+13)) >= mmc->clock * 1/4
|
2011-03-03 12:48:56 +09:00
|
|
|
* Taking log2 both the sides
|
mmc: fsl_esdhc: fix calculation of timeout for data transactions
Calculation of the timeout value should be based on actual clock value,
written to controller registers. Since mmc->tran_speed is either the
maximum allowed speed, or the preliminary value, that is be not yet
set to registers, the actual timeout, taken by the controller, based
on its clock settings, may be much longer than expected, based on
mmc->tran_speed value. In particular it happens at early initialization
stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while
actual clock setting, configured in the controller, is 400kHz.
It's more correct to use mmc->clock value for timeout calculation instead.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 16:40:41 +09:00
|
|
|
* => timeout + 13 >= log2(mmc->clock/4)
|
2011-03-03 12:48:56 +09:00
|
|
|
* Rounding up to next power of 2
|
mmc: fsl_esdhc: fix calculation of timeout for data transactions
Calculation of the timeout value should be based on actual clock value,
written to controller registers. Since mmc->tran_speed is either the
maximum allowed speed, or the preliminary value, that is be not yet
set to registers, the actual timeout, taken by the controller, based
on its clock settings, may be much longer than expected, based on
mmc->tran_speed value. In particular it happens at early initialization
stage, when typical value of mmc->tran_speed is 20MHz or 26MHz, while
actual clock setting, configured in the controller, is 400kHz.
It's more correct to use mmc->clock value for timeout calculation instead.
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
2014-03-24 16:40:41 +09:00
|
|
|
* => timeout + 13 = log2(mmc->clock/4) + 1
|
|
|
|
* => timeout + 13 = fls(mmc->clock/4)
|
2015-12-30 15:19:30 +09:00
|
|
|
*
|
|
|
|
* However, the MMC spec "It is strongly recommended for hosts to
|
|
|
|
* implement more than 500ms timeout value even if the card
|
|
|
|
* indicates the 250ms maximum busy length." Even the previous
|
|
|
|
* value of 300ms is known to be insufficient for some cards.
|
|
|
|
* So, we use
|
|
|
|
* => timeout + 13 = fls(mmc->clock/2)
|
2011-03-03 12:48:56 +09:00
|
|
|
*/
|
2015-12-30 15:19:30 +09:00
|
|
|
timeout = fls(mmc->clock/2);
|
2008-10-31 06:47:16 +09:00
|
|
|
timeout -= 13;
|
|
|
|
|
|
|
|
if (timeout > 14)
|
|
|
|
timeout = 14;
|
|
|
|
|
|
|
|
if (timeout < 0)
|
|
|
|
timeout = 0;
|
|
|
|
|
2020-10-12 17:07:13 +09:00
|
|
|
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) &&
|
|
|
|
(timeout == 4 || timeout == 8 || timeout == 12))
|
2011-01-30 06:36:10 +09:00
|
|
|
timeout++;
|
|
|
|
|
2020-10-12 17:07:13 +09:00
|
|
|
if (IS_ENABLED(ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE))
|
|
|
|
timeout = 0xE;
|
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Sends a command out on the bus. Takes the mmc pointer,
|
|
|
|
* a command pointer, and an optional data pointer.
|
|
|
|
*/
|
2017-07-30 02:35:18 +09:00
|
|
|
static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
|
|
|
|
struct mmc_cmd *cmd, struct mmc_data *data)
|
2008-10-31 06:47:16 +09:00
|
|
|
{
|
2014-03-24 16:41:06 +09:00
|
|
|
int err = 0;
|
2008-10-31 06:47:16 +09:00
|
|
|
uint xfertyp;
|
|
|
|
uint irqstat;
|
2018-01-21 20:00:24 +09:00
|
|
|
u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2018-11-19 21:31:53 +09:00
|
|
|
unsigned long start;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2020-10-12 17:07:13 +09:00
|
|
|
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111) &&
|
|
|
|
cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
|
2011-01-07 14:42:19 +09:00
|
|
|
return 0;
|
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_write32(®s->irqstat, -1);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
sync();
|
|
|
|
|
|
|
|
/* Wait for the bus to be idle */
|
2010-02-05 23:11:27 +09:00
|
|
|
while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) ||
|
|
|
|
(esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB))
|
|
|
|
;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)
|
|
|
|
;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
/* Wait at least 8 SD clock cycles before the next command */
|
|
|
|
/*
|
|
|
|
* Note: This is way more than 8 cycles, but 1ms seems to
|
|
|
|
* resolve timing issues with some cards
|
|
|
|
*/
|
|
|
|
udelay(1000);
|
|
|
|
|
|
|
|
/* Set up for a data transfer if we have one */
|
|
|
|
if (data) {
|
2017-07-30 02:35:17 +09:00
|
|
|
err = esdhc_setup_data(priv, mmc, data);
|
2008-10-31 06:47:16 +09:00
|
|
|
if(err)
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Figure out the transfer arguments */
|
|
|
|
xfertyp = esdhc_xfertyp(cmd, data);
|
|
|
|
|
fsl_esdhc: Do not clear interrupt status bits until data processed
After waiting for the command completion event, the interrupt status
bits, that occured to be set by that time, are cleared by writing them
back. It is supposed, that it should be command related bits (command
complete and may be command errors).
However, in some cases the DMA already completes by that time before
the full transaction completes. The corresponding DINT bit gets set
and then cleared before even entering the loop, waiting for data part
completion. That waiting loop never gets this bit set, causing the
operation to hang. This is reported to happen, for example, for write
operation of 1 sector to upper area (block #7400000) of SanDisk Ultra II
8GB card.
The solution could be to explicitly clear only command related interrupt
status bits. However, since subsequent processing does not rely on
any command bits state, it could be easier just to remove clearing
of any bits at that point, leaving them all until all data processing
completes. After that the whole register will be cleared at once.
Also, on occasion, interrupts masking moved to before writing the command,
just for the case there should be no chance of interrupt between the first
command and interrupts masking.
Reported-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-06-12 00:34:22 +09:00
|
|
|
/* Mask all irqs */
|
|
|
|
esdhc_write32(®s->irqsigen, 0);
|
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
/* Send the command */
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_write32(®s->cmdarg, cmd->cmdarg);
|
|
|
|
esdhc_write32(®s->xfertyp, xfertyp);
|
2012-03-26 12:13:05 +09:00
|
|
|
|
2020-09-01 17:58:01 +09:00
|
|
|
if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
|
|
|
|
cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
|
|
|
|
flags = IRQSTAT_BRR;
|
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
/* Wait for the command to complete */
|
2018-11-19 21:31:53 +09:00
|
|
|
start = get_timer(0);
|
|
|
|
while (!(esdhc_read32(®s->irqstat) & flags)) {
|
|
|
|
if (get_timer(start) > 1000) {
|
|
|
|
err = -ETIMEDOUT;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
}
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
irqstat = esdhc_read32(®s->irqstat);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2014-03-24 16:41:06 +09:00
|
|
|
if (irqstat & CMD_ERR) {
|
2016-07-19 16:33:36 +09:00
|
|
|
err = -ECOMM;
|
2014-03-24 16:41:06 +09:00
|
|
|
goto out;
|
2012-03-26 12:13:05 +09:00
|
|
|
}
|
|
|
|
|
2014-03-24 16:41:06 +09:00
|
|
|
if (irqstat & IRQSTAT_CTOE) {
|
2016-07-19 16:33:36 +09:00
|
|
|
err = -ETIMEDOUT;
|
2014-03-24 16:41:06 +09:00
|
|
|
goto out;
|
|
|
|
}
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2012-03-26 12:13:05 +09:00
|
|
|
/* Workaround for ESDHC errata ENGcm03648 */
|
|
|
|
if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
|
2015-04-15 11:13:12 +09:00
|
|
|
int timeout = 6000;
|
2012-03-26 12:13:05 +09:00
|
|
|
|
2015-04-15 11:13:12 +09:00
|
|
|
/* Poll on DATA0 line for cmd with busy signal for 600 ms */
|
2012-03-26 12:13:05 +09:00
|
|
|
while (timeout > 0 && !(esdhc_read32(®s->prsstat) &
|
|
|
|
PRSSTAT_DAT0)) {
|
|
|
|
udelay(100);
|
|
|
|
timeout--;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (timeout <= 0) {
|
|
|
|
printf("Timeout waiting for DAT0 to go high!\n");
|
2016-07-19 16:33:36 +09:00
|
|
|
err = -ETIMEDOUT;
|
2014-03-24 16:41:06 +09:00
|
|
|
goto out;
|
2012-03-26 12:13:05 +09:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
/* Copy the response to the response buffer */
|
|
|
|
if (cmd->resp_type & MMC_RSP_136) {
|
|
|
|
u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
|
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
cmdrsp3 = esdhc_read32(®s->cmdrsp3);
|
|
|
|
cmdrsp2 = esdhc_read32(®s->cmdrsp2);
|
|
|
|
cmdrsp1 = esdhc_read32(®s->cmdrsp1);
|
|
|
|
cmdrsp0 = esdhc_read32(®s->cmdrsp0);
|
2009-04-05 17:00:56 +09:00
|
|
|
cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
|
|
|
|
cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
|
|
|
|
cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
|
|
|
|
cmd->response[3] = (cmdrsp0 << 8);
|
2008-10-31 06:47:16 +09:00
|
|
|
} else
|
2010-02-05 23:11:27 +09:00
|
|
|
cmd->response[0] = esdhc_read32(®s->cmdrsp0);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
/* Wait until all of the blocks are transferred */
|
|
|
|
if (data) {
|
2020-10-12 17:07:13 +09:00
|
|
|
if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO)) {
|
|
|
|
esdhc_pio_read_write(priv, data);
|
|
|
|
} else {
|
|
|
|
flags = DATA_COMPLETE;
|
|
|
|
if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
|
|
|
|
cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
|
|
|
|
flags = IRQSTAT_BRR;
|
|
|
|
|
|
|
|
do {
|
|
|
|
irqstat = esdhc_read32(®s->irqstat);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2020-10-12 17:07:13 +09:00
|
|
|
if (irqstat & IRQSTAT_DTOE) {
|
|
|
|
err = -ETIMEDOUT;
|
|
|
|
goto out;
|
|
|
|
}
|
2010-07-31 13:45:18 +09:00
|
|
|
|
2020-10-12 17:07:13 +09:00
|
|
|
if (irqstat & DATA_ERR) {
|
|
|
|
err = -ECOMM;
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
} while ((irqstat & flags) != flags);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Need invalidate the dcache here again to avoid any
|
|
|
|
* cache-fill during the DMA operations such as the
|
|
|
|
* speculative pre-fetching etc.
|
|
|
|
*/
|
|
|
|
dma_unmap_single(priv->dma_addr,
|
|
|
|
data->blocks * data->blocksize,
|
|
|
|
mmc_get_dma_dir(data));
|
|
|
|
}
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
|
|
|
|
2014-03-24 16:41:06 +09:00
|
|
|
out:
|
|
|
|
/* Reset CMD and DATA portions on error */
|
|
|
|
if (err) {
|
|
|
|
esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) |
|
|
|
|
SYSCTL_RSTC);
|
|
|
|
while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC)
|
|
|
|
;
|
|
|
|
|
|
|
|
if (data) {
|
|
|
|
esdhc_write32(®s->sysctl,
|
|
|
|
esdhc_read32(®s->sysctl) |
|
|
|
|
SYSCTL_RSTD);
|
|
|
|
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD))
|
|
|
|
;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_write32(®s->irqstat, -1);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2014-03-24 16:41:06 +09:00
|
|
|
return err;
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:17 +09:00
|
|
|
static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
|
2008-10-31 06:47:16 +09:00
|
|
|
{
|
2018-01-17 06:44:18 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2017-05-03 18:59:03 +09:00
|
|
|
int div = 1;
|
|
|
|
int pre_div = 2;
|
2019-07-16 16:09:11 +09:00
|
|
|
unsigned int sdhc_clk = priv->sdhc_clk;
|
|
|
|
u32 time_out;
|
|
|
|
u32 value;
|
2008-10-31 06:47:16 +09:00
|
|
|
uint clk;
|
|
|
|
|
2014-03-12 02:34:20 +09:00
|
|
|
if (clock < mmc->cfg->f_min)
|
|
|
|
clock = mmc->cfg->f_min;
|
2010-02-05 23:11:27 +09:00
|
|
|
|
2019-10-21 19:09:09 +09:00
|
|
|
while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
|
2019-05-08 00:47:28 +09:00
|
|
|
pre_div *= 2;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2019-10-21 19:09:09 +09:00
|
|
|
while (sdhc_clk / (div * pre_div) > clock && div < 16)
|
2019-05-08 00:47:28 +09:00
|
|
|
div++;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2021-03-17 23:01:36 +09:00
|
|
|
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A011334) &&
|
|
|
|
clock == 200000000 && mmc->selected_mode == MMC_HS_400) {
|
|
|
|
u32 div_ratio = pre_div * div;
|
|
|
|
|
|
|
|
if (div_ratio <= 4) {
|
|
|
|
pre_div = 4;
|
|
|
|
div = 1;
|
|
|
|
} else if (div_ratio <= 8) {
|
|
|
|
pre_div = 4;
|
|
|
|
div = 2;
|
|
|
|
} else if (div_ratio <= 12) {
|
|
|
|
pre_div = 4;
|
|
|
|
div = 3;
|
|
|
|
} else {
|
|
|
|
printf("unsupported clock division.\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-09-01 17:58:06 +09:00
|
|
|
mmc->clock = sdhc_clk / pre_div / div;
|
|
|
|
priv->clock = mmc->clock;
|
|
|
|
|
2017-05-03 18:59:03 +09:00
|
|
|
pre_div >>= 1;
|
2008-10-31 06:47:16 +09:00
|
|
|
div -= 1;
|
|
|
|
|
|
|
|
clk = (pre_div << 8) | (div << 4);
|
|
|
|
|
2010-03-19 05:51:05 +09:00
|
|
|
esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
|
2010-02-05 23:11:27 +09:00
|
|
|
|
|
|
|
esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2019-07-16 16:09:11 +09:00
|
|
|
time_out = 20;
|
|
|
|
value = PRSSTAT_SDSTB;
|
|
|
|
while (!(esdhc_read32(®s->prsstat) & value)) {
|
|
|
|
if (time_out == 0) {
|
|
|
|
printf("fsl_esdhc: Internal clock never stabilised.\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
time_out--;
|
|
|
|
mdelay(1);
|
|
|
|
}
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2015-12-05 04:32:48 +09:00
|
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:17 +09:00
|
|
|
static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
|
2015-04-22 14:57:40 +09:00
|
|
|
{
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2015-04-22 14:57:40 +09:00
|
|
|
u32 value;
|
|
|
|
u32 time_out;
|
|
|
|
|
|
|
|
value = esdhc_read32(®s->sysctl);
|
|
|
|
|
|
|
|
if (enable)
|
|
|
|
value |= SYSCTL_CKEN;
|
|
|
|
else
|
|
|
|
value &= ~SYSCTL_CKEN;
|
|
|
|
|
|
|
|
esdhc_write32(®s->sysctl, value);
|
|
|
|
|
|
|
|
time_out = 20;
|
|
|
|
value = PRSSTAT_SDSTB;
|
|
|
|
while (!(esdhc_read32(®s->prsstat) & value)) {
|
|
|
|
if (time_out == 0) {
|
|
|
|
printf("fsl_esdhc: Internal clock never stabilised.\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
time_out--;
|
|
|
|
mdelay(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-09-01 17:58:05 +09:00
|
|
|
static void esdhc_flush_async_fifo(struct fsl_esdhc_priv *priv)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
|
u32 time_out;
|
|
|
|
|
|
|
|
esdhc_setbits32(®s->esdhcctl, ESDHCCTL_FAF);
|
|
|
|
|
|
|
|
time_out = 20;
|
|
|
|
while (esdhc_read32(®s->esdhcctl) & ESDHCCTL_FAF) {
|
|
|
|
if (time_out == 0) {
|
|
|
|
printf("fsl_esdhc: Flush asynchronous FIFO timeout.\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
time_out--;
|
|
|
|
mdelay(1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void esdhc_tuning_block_enable(struct fsl_esdhc_priv *priv,
|
|
|
|
bool en)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
|
|
|
|
|
esdhc_clock_control(priv, false);
|
|
|
|
esdhc_flush_async_fifo(priv);
|
|
|
|
if (en)
|
|
|
|
esdhc_setbits32(®s->tbctl, TBCTL_TB_EN);
|
|
|
|
else
|
|
|
|
esdhc_clrbits32(®s->tbctl, TBCTL_TB_EN);
|
|
|
|
esdhc_clock_control(priv, true);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void esdhc_exit_hs400(struct fsl_esdhc_priv *priv)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
|
|
|
|
|
|
|
esdhc_clrbits32(®s->sdtimingctl, FLW_CTL_BG);
|
|
|
|
esdhc_clrbits32(®s->sdclkctl, CMD_CLK_CTL);
|
|
|
|
|
|
|
|
esdhc_clock_control(priv, false);
|
|
|
|
esdhc_clrbits32(®s->tbctl, HS400_MODE);
|
|
|
|
esdhc_clock_control(priv, true);
|
|
|
|
|
|
|
|
esdhc_clrbits32(®s->dllcfg0, DLL_FREQ_SEL | DLL_ENABLE);
|
|
|
|
esdhc_clrbits32(®s->tbctl, HS400_WNDW_ADJUST);
|
|
|
|
|
|
|
|
esdhc_tuning_block_enable(priv, false);
|
|
|
|
}
|
|
|
|
|
2020-10-20 12:04:52 +09:00
|
|
|
static int esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode)
|
2020-09-01 17:58:01 +09:00
|
|
|
{
|
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2020-10-20 12:04:52 +09:00
|
|
|
ulong start;
|
|
|
|
u32 val;
|
2020-09-01 17:58:01 +09:00
|
|
|
|
2020-09-01 17:58:05 +09:00
|
|
|
/* Exit HS400 mode before setting any other mode */
|
|
|
|
if (esdhc_read32(®s->tbctl) & HS400_MODE &&
|
|
|
|
mode != MMC_HS_400)
|
|
|
|
esdhc_exit_hs400(priv);
|
|
|
|
|
2020-09-01 17:58:01 +09:00
|
|
|
esdhc_clock_control(priv, false);
|
|
|
|
|
|
|
|
if (mode == MMC_HS_200)
|
|
|
|
esdhc_clrsetbits32(®s->autoc12err, UHSM_MASK,
|
|
|
|
UHSM_SDR104_HS200);
|
2020-09-01 17:58:05 +09:00
|
|
|
if (mode == MMC_HS_400) {
|
|
|
|
esdhc_setbits32(®s->tbctl, HS400_MODE);
|
|
|
|
esdhc_setbits32(®s->sdclkctl, CMD_CLK_CTL);
|
|
|
|
esdhc_clock_control(priv, true);
|
2020-09-01 17:58:01 +09:00
|
|
|
|
2020-09-01 17:58:07 +09:00
|
|
|
if (priv->clock == 200000000)
|
|
|
|
esdhc_setbits32(®s->dllcfg0, DLL_FREQ_SEL);
|
|
|
|
|
|
|
|
esdhc_setbits32(®s->dllcfg0, DLL_ENABLE);
|
2020-10-20 12:04:52 +09:00
|
|
|
|
|
|
|
esdhc_setbits32(®s->dllcfg0, DLL_RESET);
|
|
|
|
udelay(1);
|
|
|
|
esdhc_clrbits32(®s->dllcfg0, DLL_RESET);
|
|
|
|
|
|
|
|
start = get_timer(0);
|
|
|
|
val = DLL_STS_SLV_LOCK;
|
|
|
|
while (!(esdhc_read32(®s->dllstat0) & val)) {
|
|
|
|
if (get_timer(start) > 1000) {
|
|
|
|
printf("fsl_esdhc: delay chain lock timeout\n");
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-09-01 17:58:05 +09:00
|
|
|
esdhc_setbits32(®s->tbctl, HS400_WNDW_ADJUST);
|
|
|
|
|
|
|
|
esdhc_clock_control(priv, false);
|
|
|
|
esdhc_flush_async_fifo(priv);
|
|
|
|
}
|
2020-09-01 17:58:01 +09:00
|
|
|
esdhc_clock_control(priv, true);
|
2020-10-20 12:04:52 +09:00
|
|
|
return 0;
|
2020-09-01 17:58:01 +09:00
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:18 +09:00
|
|
|
static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
|
2008-10-31 06:47:16 +09:00
|
|
|
{
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2020-10-20 12:04:52 +09:00
|
|
|
int ret;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2019-12-19 19:59:30 +09:00
|
|
|
if (priv->is_sdhc_per_clk) {
|
|
|
|
/* Select to use peripheral clock */
|
|
|
|
esdhc_clock_control(priv, false);
|
|
|
|
esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS);
|
|
|
|
esdhc_clock_control(priv, true);
|
|
|
|
}
|
|
|
|
|
2020-09-01 17:58:05 +09:00
|
|
|
if (mmc->selected_mode == MMC_HS_400)
|
|
|
|
esdhc_tuning_block_enable(priv, true);
|
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
/* Set the clock speed */
|
2018-01-21 20:00:24 +09:00
|
|
|
if (priv->clock != mmc->clock)
|
|
|
|
set_sysctl(priv, mmc, mmc->clock);
|
|
|
|
|
2020-09-01 17:58:01 +09:00
|
|
|
/* Set timing */
|
2020-10-20 12:04:52 +09:00
|
|
|
ret = esdhc_set_timing(priv, mmc->selected_mode);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2020-09-01 17:58:01 +09:00
|
|
|
|
2008-10-31 06:47:16 +09:00
|
|
|
/* Set the bus width */
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
if (mmc->bus_width == 4)
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_setbits32(®s->proctl, PROCTL_DTW_4);
|
2008-10-31 06:47:16 +09:00
|
|
|
else if (mmc->bus_width == 8)
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_setbits32(®s->proctl, PROCTL_DTW_8);
|
|
|
|
|
2016-12-30 15:30:16 +09:00
|
|
|
return 0;
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
|
|
|
|
2020-01-30 21:06:45 +09:00
|
|
|
static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_ARCH_MPC830X
|
|
|
|
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
|
|
|
|
sysconf83xx_t *sysconf = &immr->sysconf;
|
|
|
|
|
|
|
|
setbits_be32(&sysconf->sdhccr, 0x02000000);
|
|
|
|
#else
|
|
|
|
esdhc_write32(®s->esdhcctl, 0x00000040);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:18 +09:00
|
|
|
static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
|
2008-10-31 06:47:16 +09:00
|
|
|
{
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2017-07-30 02:35:20 +09:00
|
|
|
ulong start;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
/* Reset the entire host controller */
|
2013-07-15 22:44:29 +09:00
|
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
|
2010-02-05 23:11:27 +09:00
|
|
|
|
|
|
|
/* Wait until the controller is available */
|
2017-07-30 02:35:20 +09:00
|
|
|
start = get_timer(0);
|
|
|
|
while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) {
|
|
|
|
if (get_timer(start) > 1000)
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2020-09-01 17:58:02 +09:00
|
|
|
/* Clean TBCTL[TB_EN] which is not able to be reset by reset all */
|
|
|
|
esdhc_clrbits32(®s->tbctl, TBCTL_TB_EN);
|
|
|
|
|
2020-01-30 21:06:45 +09:00
|
|
|
esdhc_enable_cache_snooping(regs);
|
2010-12-04 14:07:23 +09:00
|
|
|
|
2013-07-15 22:44:29 +09:00
|
|
|
esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
/* Set the initial clock speed */
|
2020-10-20 12:04:51 +09:00
|
|
|
set_sysctl(priv, mmc, 400000);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
/* Disable the BRR and BWR bits in IRQSTAT */
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
|
|
|
/* Put the PROCTL reg back to the default */
|
2010-02-05 23:11:27 +09:00
|
|
|
esdhc_write32(®s->proctl, PROCTL_INIT);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
/* Set timout to the maximum value */
|
|
|
|
esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2021-03-17 23:01:37 +09:00
|
|
|
if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND))
|
|
|
|
esdhc_clrbits32(®s->dllcfg1, DLL_PD_PULSE_STRETCH_SEL);
|
|
|
|
|
2012-01-02 10:15:38 +09:00
|
|
|
return 0;
|
|
|
|
}
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2017-07-30 02:35:18 +09:00
|
|
|
static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
|
2012-01-02 10:15:38 +09:00
|
|
|
{
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2012-01-02 10:15:38 +09:00
|
|
|
|
2014-01-10 14:52:17 +09:00
|
|
|
#ifdef CONFIG_ESDHC_DETECT_QUIRK
|
|
|
|
if (CONFIG_ESDHC_DETECT_QUIRK)
|
|
|
|
return 1;
|
|
|
|
#endif
|
2020-05-19 12:06:43 +09:00
|
|
|
if (esdhc_read32(®s->prsstat) & PRSSTAT_CINS)
|
|
|
|
return 1;
|
2010-02-05 23:11:27 +09:00
|
|
|
|
2020-05-19 12:06:43 +09:00
|
|
|
return 0;
|
2008-10-31 06:47:16 +09:00
|
|
|
}
|
|
|
|
|
2019-10-31 19:54:23 +09:00
|
|
|
static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
|
|
|
|
struct mmc_config *cfg)
|
2008-10-31 06:47:16 +09:00
|
|
|
{
|
2019-10-31 19:54:23 +09:00
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2019-10-31 19:54:21 +09:00
|
|
|
u32 caps;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2014-09-05 14:52:40 +09:00
|
|
|
caps = esdhc_read32(®s->hostcapblt);
|
2020-10-12 17:07:13 +09:00
|
|
|
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
|
|
|
|
caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
|
|
|
|
if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33))
|
|
|
|
caps |= HOSTCAPBLT_VS33;
|
2019-10-31 19:54:21 +09:00
|
|
|
if (caps & HOSTCAPBLT_VS18)
|
|
|
|
cfg->voltages |= MMC_VDD_165_195;
|
|
|
|
if (caps & HOSTCAPBLT_VS30)
|
|
|
|
cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
|
|
|
|
if (caps & HOSTCAPBLT_VS33)
|
|
|
|
cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
|
2010-11-26 02:06:09 +09:00
|
|
|
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->name = "FSL_SDHC";
|
2013-03-25 18:13:34 +09:00
|
|
|
|
2019-10-31 19:54:21 +09:00
|
|
|
if (caps & HOSTCAPBLT_HSS)
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
2008-10-31 06:47:16 +09:00
|
|
|
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->f_min = 400000;
|
2018-01-21 20:00:24 +09:00
|
|
|
cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
|
2017-07-30 02:35:21 +09:00
|
|
|
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
2016-03-25 15:16:56 +09:00
|
|
|
}
|
|
|
|
|
2010-02-05 23:11:27 +09:00
|
|
|
#ifdef CONFIG_OF_LIBFDT
|
2017-01-17 11:43:54 +09:00
|
|
|
__weak int esdhc_status_fixup(void *blob, const char *compat)
|
2009-06-10 05:25:29 +09:00
|
|
|
{
|
2020-10-12 17:07:13 +09:00
|
|
|
if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) {
|
2011-01-04 18:23:05 +09:00
|
|
|
do_fixup_by_compat(blob, compat, "status", "disabled",
|
2017-01-17 11:43:54 +09:00
|
|
|
sizeof("disabled"), 1);
|
|
|
|
return 1;
|
2009-06-10 05:25:29 +09:00
|
|
|
}
|
2020-10-12 17:07:13 +09:00
|
|
|
|
2017-01-17 11:43:54 +09:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-05-19 12:06:44 +09:00
|
|
|
|
2020-10-12 17:07:13 +09:00
|
|
|
#if CONFIG_IS_ENABLED(DM_MMC)
|
|
|
|
static int fsl_esdhc_get_cd(struct udevice *dev);
|
2020-05-19 12:06:44 +09:00
|
|
|
static void esdhc_disable_for_no_card(void *blob)
|
|
|
|
{
|
|
|
|
struct udevice *dev;
|
|
|
|
|
|
|
|
for (uclass_first_device(UCLASS_MMC, &dev);
|
|
|
|
dev;
|
|
|
|
uclass_next_device(&dev)) {
|
|
|
|
char esdhc_path[50];
|
|
|
|
|
|
|
|
if (fsl_esdhc_get_cd(dev))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
snprintf(esdhc_path, sizeof(esdhc_path), "/soc/esdhc@%lx",
|
|
|
|
(unsigned long)dev_read_addr(dev));
|
|
|
|
do_fixup_by_path(blob, esdhc_path, "status", "disabled",
|
|
|
|
sizeof("disabled"), 1);
|
|
|
|
}
|
|
|
|
}
|
2020-10-12 17:07:13 +09:00
|
|
|
#else
|
|
|
|
static void esdhc_disable_for_no_card(void *blob)
|
|
|
|
{
|
|
|
|
}
|
2020-05-19 12:06:44 +09:00
|
|
|
#endif
|
|
|
|
|
2020-06-26 15:13:33 +09:00
|
|
|
void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
|
2017-01-17 11:43:54 +09:00
|
|
|
{
|
|
|
|
const char *compat = "fsl,esdhc";
|
|
|
|
|
|
|
|
if (esdhc_status_fixup(blob, compat))
|
|
|
|
return;
|
2020-10-12 17:07:13 +09:00
|
|
|
|
|
|
|
if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND))
|
|
|
|
esdhc_disable_for_no_card(blob);
|
|
|
|
|
2009-06-10 05:25:29 +09:00
|
|
|
do_fixup_by_compat_u32(blob, compat, "clock-frequency",
|
2012-12-14 05:49:05 +09:00
|
|
|
gd->arch.sdhc_clk, 1);
|
2009-06-10 05:25:29 +09:00
|
|
|
}
|
2010-02-05 23:11:27 +09:00
|
|
|
#endif
|
2016-03-25 15:16:56 +09:00
|
|
|
|
2019-10-31 19:54:26 +09:00
|
|
|
#if !CONFIG_IS_ENABLED(DM_MMC)
|
|
|
|
static int esdhc_getcd(struct mmc *mmc)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc_priv *priv = mmc->priv;
|
|
|
|
|
|
|
|
return esdhc_getcd_common(priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int esdhc_init(struct mmc *mmc)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc_priv *priv = mmc->priv;
|
|
|
|
|
|
|
|
return esdhc_init_common(priv, mmc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
|
|
|
|
struct mmc_data *data)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc_priv *priv = mmc->priv;
|
|
|
|
|
|
|
|
return esdhc_send_cmd_common(priv, mmc, cmd, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int esdhc_set_ios(struct mmc *mmc)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc_priv *priv = mmc->priv;
|
|
|
|
|
|
|
|
return esdhc_set_ios_common(priv, mmc);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct mmc_ops esdhc_ops = {
|
|
|
|
.getcd = esdhc_getcd,
|
|
|
|
.init = esdhc_init,
|
|
|
|
.send_cmd = esdhc_send_cmd,
|
|
|
|
.set_ios = esdhc_set_ios,
|
|
|
|
};
|
|
|
|
|
2020-06-26 15:13:33 +09:00
|
|
|
int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
|
2019-10-31 19:54:26 +09:00
|
|
|
{
|
|
|
|
struct fsl_esdhc_plat *plat;
|
|
|
|
struct fsl_esdhc_priv *priv;
|
|
|
|
struct mmc_config *mmc_cfg;
|
|
|
|
struct mmc *mmc;
|
|
|
|
|
|
|
|
if (!cfg)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
|
|
|
|
if (!priv)
|
|
|
|
return -ENOMEM;
|
|
|
|
plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
|
|
|
|
if (!plat) {
|
|
|
|
free(priv);
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
|
|
|
|
priv->sdhc_clk = cfg->sdhc_clk;
|
2019-12-19 19:59:30 +09:00
|
|
|
if (gd->arch.sdhc_per_clk)
|
|
|
|
priv->is_sdhc_per_clk = true;
|
2019-10-31 19:54:26 +09:00
|
|
|
|
|
|
|
mmc_cfg = &plat->cfg;
|
|
|
|
|
|
|
|
if (cfg->max_bus_width == 8) {
|
|
|
|
mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
|
|
|
|
MMC_MODE_8BIT;
|
|
|
|
} else if (cfg->max_bus_width == 4) {
|
|
|
|
mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT;
|
|
|
|
} else if (cfg->max_bus_width == 1) {
|
|
|
|
mmc_cfg->host_caps |= MMC_MODE_1BIT;
|
|
|
|
} else {
|
|
|
|
mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
|
|
|
|
MMC_MODE_8BIT;
|
|
|
|
printf("No max bus width provided. Assume 8-bit supported.\n");
|
|
|
|
}
|
|
|
|
|
2020-10-12 17:07:13 +09:00
|
|
|
if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK))
|
2019-10-31 19:54:26 +09:00
|
|
|
mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
|
2020-10-12 17:07:13 +09:00
|
|
|
|
2019-10-31 19:54:26 +09:00
|
|
|
mmc_cfg->ops = &esdhc_ops;
|
|
|
|
|
|
|
|
fsl_esdhc_get_cfg_common(priv, mmc_cfg);
|
|
|
|
|
|
|
|
mmc = mmc_create(mmc_cfg, priv);
|
|
|
|
if (!mmc)
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
priv->mmc = mmc;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-06-26 15:13:33 +09:00
|
|
|
int fsl_esdhc_mmc_init(struct bd_info *bis)
|
2019-10-31 19:54:26 +09:00
|
|
|
{
|
|
|
|
struct fsl_esdhc_cfg *cfg;
|
|
|
|
|
|
|
|
cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
|
|
|
|
cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
|
2019-12-19 19:59:30 +09:00
|
|
|
/* Prefer peripheral clock which provides higher frequency. */
|
|
|
|
if (gd->arch.sdhc_per_clk)
|
|
|
|
cfg->sdhc_clk = gd->arch.sdhc_per_clk;
|
|
|
|
else
|
|
|
|
cfg->sdhc_clk = gd->arch.sdhc_clk;
|
2019-10-31 19:54:26 +09:00
|
|
|
return fsl_esdhc_initialize(bis, cfg);
|
|
|
|
}
|
|
|
|
#else /* DM_MMC */
|
2016-03-25 15:16:56 +09:00
|
|
|
static int fsl_esdhc_probe(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
2020-12-04 08:55:20 +09:00
|
|
|
struct fsl_esdhc_plat *plat = dev_get_plat(dev);
|
2016-03-25 15:16:56 +09:00
|
|
|
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
2020-10-12 17:07:14 +09:00
|
|
|
u32 caps, hostver;
|
2016-03-25 15:16:56 +09:00
|
|
|
fdt_addr_t addr;
|
2017-07-30 02:35:24 +09:00
|
|
|
struct mmc *mmc;
|
2020-05-19 12:06:44 +09:00
|
|
|
int ret;
|
2016-03-25 15:16:56 +09:00
|
|
|
|
2017-07-30 02:35:23 +09:00
|
|
|
addr = dev_read_addr(dev);
|
2016-03-25 15:16:56 +09:00
|
|
|
if (addr == FDT_ADDR_T_NONE)
|
|
|
|
return -EINVAL;
|
2019-04-11 20:01:50 +09:00
|
|
|
#ifdef CONFIG_PPC
|
|
|
|
priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
|
|
|
|
#else
|
2016-03-25 15:16:56 +09:00
|
|
|
priv->esdhc_regs = (struct fsl_esdhc *)addr;
|
2019-04-11 20:01:50 +09:00
|
|
|
#endif
|
2016-03-25 15:16:56 +09:00
|
|
|
priv->dev = dev;
|
|
|
|
|
2020-10-12 17:07:14 +09:00
|
|
|
if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2)) {
|
|
|
|
/*
|
|
|
|
* Only newer eSDHC controllers can do ADMA2 if the ADMA flag
|
|
|
|
* is set in the host capabilities register.
|
|
|
|
*/
|
|
|
|
caps = esdhc_read32(&priv->esdhc_regs->hostcapblt);
|
|
|
|
hostver = esdhc_read32(&priv->esdhc_regs->hostver);
|
|
|
|
if (caps & HOSTCAPBLT_DMAS &&
|
|
|
|
HOSTVER_VENDOR(hostver) > VENDOR_V_22) {
|
|
|
|
priv->adma_desc_table = sdhci_adma_init();
|
|
|
|
if (!priv->adma_desc_table)
|
|
|
|
debug("Could not allocate ADMA tables, falling back to SDMA\n");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-12-19 19:59:30 +09:00
|
|
|
if (gd->arch.sdhc_per_clk) {
|
|
|
|
priv->sdhc_clk = gd->arch.sdhc_per_clk;
|
|
|
|
priv->is_sdhc_per_clk = true;
|
|
|
|
} else {
|
|
|
|
priv->sdhc_clk = gd->arch.sdhc_clk;
|
|
|
|
}
|
|
|
|
|
2019-11-12 20:28:36 +09:00
|
|
|
if (priv->sdhc_clk <= 0) {
|
|
|
|
dev_err(dev, "Unable to get clk for %s\n", dev->name);
|
|
|
|
return -EINVAL;
|
2016-03-25 15:16:56 +09:00
|
|
|
}
|
|
|
|
|
2019-10-31 19:54:23 +09:00
|
|
|
fsl_esdhc_get_cfg_common(priv, &plat->cfg);
|
2016-03-25 15:16:56 +09:00
|
|
|
|
2019-07-16 16:09:11 +09:00
|
|
|
mmc_of_parse(dev, &plat->cfg);
|
|
|
|
|
2017-07-30 02:35:24 +09:00
|
|
|
mmc = &plat->mmc;
|
|
|
|
mmc->cfg = &plat->cfg;
|
|
|
|
mmc->dev = dev;
|
2019-05-23 12:05:46 +09:00
|
|
|
|
2017-07-30 02:35:24 +09:00
|
|
|
upriv->mmc = mmc;
|
2016-03-25 15:16:56 +09:00
|
|
|
|
2020-05-19 12:06:44 +09:00
|
|
|
ret = esdhc_init_common(priv, mmc);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
2020-10-12 17:07:13 +09:00
|
|
|
if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND) &&
|
|
|
|
!fsl_esdhc_get_cd(dev))
|
2020-05-19 12:06:44 +09:00
|
|
|
esdhc_setbits32(&priv->esdhc_regs->proctl, PROCTL_VOLT_SEL);
|
2020-10-12 17:07:13 +09:00
|
|
|
|
2020-05-19 12:06:44 +09:00
|
|
|
return 0;
|
2016-03-25 15:16:56 +09:00
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:24 +09:00
|
|
|
static int fsl_esdhc_get_cd(struct udevice *dev)
|
|
|
|
{
|
2020-12-04 08:55:20 +09:00
|
|
|
struct fsl_esdhc_plat *plat = dev_get_plat(dev);
|
2017-07-30 02:35:24 +09:00
|
|
|
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
|
|
2019-10-31 19:54:24 +09:00
|
|
|
if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
|
|
|
|
return 1;
|
|
|
|
|
2017-07-30 02:35:24 +09:00
|
|
|
return esdhc_getcd_common(priv);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
|
|
|
|
struct mmc_data *data)
|
|
|
|
{
|
2020-12-04 08:55:20 +09:00
|
|
|
struct fsl_esdhc_plat *plat = dev_get_plat(dev);
|
2017-07-30 02:35:24 +09:00
|
|
|
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int fsl_esdhc_set_ios(struct udevice *dev)
|
|
|
|
{
|
2020-12-04 08:55:20 +09:00
|
|
|
struct fsl_esdhc_plat *plat = dev_get_plat(dev);
|
2017-07-30 02:35:24 +09:00
|
|
|
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
return esdhc_set_ios_common(priv, &plat->mmc);
|
|
|
|
}
|
|
|
|
|
2020-09-01 17:58:00 +09:00
|
|
|
static int fsl_esdhc_reinit(struct udevice *dev)
|
|
|
|
{
|
2020-12-04 08:55:20 +09:00
|
|
|
struct fsl_esdhc_plat *plat = dev_get_plat(dev);
|
2020-09-01 17:58:00 +09:00
|
|
|
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
return esdhc_init_common(priv, &plat->mmc);
|
|
|
|
}
|
|
|
|
|
2020-09-01 17:58:01 +09:00
|
|
|
#ifdef MMC_SUPPORTS_TUNING
|
|
|
|
static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
|
|
|
|
{
|
2020-12-04 08:55:20 +09:00
|
|
|
struct fsl_esdhc_plat *plat = dev_get_plat(dev);
|
2020-09-01 17:58:01 +09:00
|
|
|
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
|
struct fsl_esdhc *regs = priv->esdhc_regs;
|
2021-03-17 23:01:36 +09:00
|
|
|
struct mmc *mmc = &plat->mmc;
|
2020-09-01 17:58:01 +09:00
|
|
|
u32 val, irqstaten;
|
|
|
|
int i;
|
|
|
|
|
2021-03-17 23:01:36 +09:00
|
|
|
if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A011334) &&
|
|
|
|
plat->mmc.hs400_tuning)
|
|
|
|
set_sysctl(priv, mmc, mmc->clock);
|
|
|
|
|
2020-09-01 17:58:01 +09:00
|
|
|
esdhc_tuning_block_enable(priv, true);
|
|
|
|
esdhc_setbits32(®s->autoc12err, EXECUTE_TUNING);
|
|
|
|
|
|
|
|
irqstaten = esdhc_read32(®s->irqstaten);
|
|
|
|
esdhc_write32(®s->irqstaten, IRQSTATEN_BRR);
|
|
|
|
|
|
|
|
for (i = 0; i < MAX_TUNING_LOOP; i++) {
|
2021-03-17 23:01:36 +09:00
|
|
|
mmc_send_tuning(mmc, opcode, NULL);
|
2020-09-01 17:58:01 +09:00
|
|
|
mdelay(1);
|
|
|
|
|
|
|
|
val = esdhc_read32(®s->autoc12err);
|
|
|
|
if (!(val & EXECUTE_TUNING)) {
|
|
|
|
if (val & SMPCLKSEL)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
esdhc_write32(®s->irqstaten, irqstaten);
|
|
|
|
|
2020-09-01 17:58:05 +09:00
|
|
|
if (i != MAX_TUNING_LOOP) {
|
|
|
|
if (plat->mmc.hs400_tuning)
|
|
|
|
esdhc_setbits32(®s->sdtimingctl, FLW_CTL_BG);
|
2020-09-01 17:58:01 +09:00
|
|
|
return 0;
|
2020-09-01 17:58:05 +09:00
|
|
|
}
|
2020-09-01 17:58:01 +09:00
|
|
|
|
|
|
|
printf("fsl_esdhc: tuning failed!\n");
|
|
|
|
esdhc_clrbits32(®s->autoc12err, SMPCLKSEL);
|
|
|
|
esdhc_clrbits32(®s->autoc12err, EXECUTE_TUNING);
|
|
|
|
esdhc_tuning_block_enable(priv, false);
|
|
|
|
return -ETIMEDOUT;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2020-09-01 17:58:05 +09:00
|
|
|
int fsl_esdhc_hs400_prepare_ddr(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
esdhc_tuning_block_enable(priv, false);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-07-30 02:35:24 +09:00
|
|
|
static const struct dm_mmc_ops fsl_esdhc_ops = {
|
|
|
|
.get_cd = fsl_esdhc_get_cd,
|
|
|
|
.send_cmd = fsl_esdhc_send_cmd,
|
|
|
|
.set_ios = fsl_esdhc_set_ios,
|
2019-07-16 16:09:11 +09:00
|
|
|
#ifdef MMC_SUPPORTS_TUNING
|
|
|
|
.execute_tuning = fsl_esdhc_execute_tuning,
|
|
|
|
#endif
|
2020-09-01 17:58:00 +09:00
|
|
|
.reinit = fsl_esdhc_reinit,
|
2020-09-01 17:58:05 +09:00
|
|
|
.hs400_prepare_ddr = fsl_esdhc_hs400_prepare_ddr,
|
2017-07-30 02:35:24 +09:00
|
|
|
};
|
|
|
|
|
2016-03-25 15:16:56 +09:00
|
|
|
static const struct udevice_id fsl_esdhc_ids[] = {
|
2016-12-07 12:54:31 +09:00
|
|
|
{ .compatible = "fsl,esdhc", },
|
2016-03-25 15:16:56 +09:00
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
|
2017-07-30 02:35:24 +09:00
|
|
|
static int fsl_esdhc_bind(struct udevice *dev)
|
|
|
|
{
|
2020-12-04 08:55:20 +09:00
|
|
|
struct fsl_esdhc_plat *plat = dev_get_plat(dev);
|
2017-07-30 02:35:24 +09:00
|
|
|
|
|
|
|
return mmc_bind(dev, &plat->mmc, &plat->cfg);
|
|
|
|
}
|
|
|
|
|
2016-03-25 15:16:56 +09:00
|
|
|
U_BOOT_DRIVER(fsl_esdhc) = {
|
|
|
|
.name = "fsl-esdhc-mmc",
|
|
|
|
.id = UCLASS_MMC,
|
|
|
|
.of_match = fsl_esdhc_ids,
|
2017-07-30 02:35:24 +09:00
|
|
|
.ops = &fsl_esdhc_ops,
|
|
|
|
.bind = fsl_esdhc_bind,
|
2016-03-25 15:16:56 +09:00
|
|
|
.probe = fsl_esdhc_probe,
|
2020-12-04 08:55:18 +09:00
|
|
|
.plat_auto = sizeof(struct fsl_esdhc_plat),
|
2020-12-04 08:55:17 +09:00
|
|
|
.priv_auto = sizeof(struct fsl_esdhc_priv),
|
2016-03-25 15:16:56 +09:00
|
|
|
};
|
|
|
|
#endif
|