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58b5e9c227
HW board design may not support the L1.1 ASPM, although the L1.1 ASPM can be supported by the SOC chip. So, export one property to disable L1.1 ASPM supported or not. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Jun Li <jun.li@nxp.com> (cherry picked from commit 7bd2d56b72d33e223305aa2ef9046c0e38f225e6) (cherry picked from commit 439d54d4021a0cc2a297472fde38de98b687e16a) Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
140 lines
5.3 KiB
Plaintext
140 lines
5.3 KiB
Plaintext
* Freescale i.MX6 PCIe interface
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This PCIe host controller is based on the Synopsys DesignWare PCIe IP
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and thus inherits all the common properties defined in designware-pcie.txt.
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Required properties:
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- compatible:
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- "fsl,imx6q-pcie"
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- "fsl,imx6sx-pcie",
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- "fsl,imx6qp-pcie"
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- "fsl,imx7d-pcie"
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- "fsl,imx8mq-pcie"
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- "fsl,imx8mm-pcie"
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- "fsl,imx8qm-pcie"
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- "fsl,imx8qxp-pcie"
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- "fsl,imx8mp-pcie"
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- "fsl,imx6q-pcie-ep"
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- "fsl,imx6sx-pcie-ep",
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- "fsl,imx6qp-pcie-ep"
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- "fsl,imx7d-pcie-ep"
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- "fsl,imx8mq-pcie-ep"
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- "fsl,imx8mm-pcie-ep"
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- "fsl,imx8qm-pcie-ep"
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- "fsl,imx8qxp-pcie-ep"
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- "fsl,imx8mp-pcie-ep"
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- reg: base address and length of the PCIe controller
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- interrupts: A list of interrupt outputs of the controller. Must contain an
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entry for each entry in the interrupt-names property.
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- interrupt-names: Must include the following entries:
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- "msi": The interrupt that is asserted when an MSI is received
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- clock-names: Must include the following additional entries:
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- "pcie_phy"
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Optional properties:
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- fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
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- fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0
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- fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20
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- fsl,tx-swing-full: Gen2 TX SWING FULL value. Default: 127
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- fsl,tx-swing-low: TX launch amplitude swing_low value. Default: 127
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- fsl,max-link-speed: Specify PCI gen for link capability. Must be '2' for
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gen2, otherwise will default to gen1. Note that the IMX6 LVDS clock outputs
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do not meet gen2 jitter requirements and thus for gen2 capability a gen2
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compliant clock generator should be used and configured.
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- reset-gpio: Should specify the GPIO for controlling the PCI bus device reset
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signal. It's not polarity aware and defaults to active-low reset sequence
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(L=reset state, H=operation state).
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- reset-gpio-active-high: If present then the reset sequence using the GPIO
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specified in the "reset-gpio" property is reversed (H=reset state,
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L=operation state).
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- vpcie-supply: Should specify the regulator in charge of PCIe port power.
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The regulator will be enabled when initializing the PCIe host and
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disabled either as part of the init process or when shutting down the
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host.
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- ext_osc: use the external oscillator as ref clock( 1: external OSC is
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used, 0 internal PLL is used).
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- hard_wired: the PCIe port is hard wired to the EP device(0: one slot
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is connected).
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- reserved-region: one reserved no-map memory used by PCIe EP/RC
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validation system.
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- interrupt-names: Optional include the following entries:
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- "dma": The interrupt that is asserted when an DMA interrupter
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is received
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- l1ss-disabled: Force to disable L1SS or not. If present then the L1
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substate would be force disabled although it might be supported by the
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chip.
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Additional required properties for imx6sx-pcie:
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- clock names: Must include the following additional entries:
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- "pcie_inbound_axi"
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- power-domains: Must be set to phandles pointing to the DISPLAY and
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PCIE_PHY power domains
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- power-domain-names: Must be "pcie", "pcie_phy"
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Additional required properties for imx7d-pcie and imx8mq-pcie:
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- power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
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- resets: Must contain phandles to PCIe-related reset lines exposed by SRC
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IP block
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- reset-names: Must contain the following entries:
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- "pciephy"
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- "apps"
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- "turnoff"
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- fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node.
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- fsl,imx8mp-hsio-mix: A phandle to an fsl,imx8mp-hsio-mix node.
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Additional required properties for imx8mq-pcie:
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- clock-names: Must include the following additional entries:
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- "pcie_aux"
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Additional required properties to enable L1sub for imx8mq-pcie, imx8mm-pcie
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and imx8mp-pcie:
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- reset-names: Must contain the following entries:
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- "clkreq"
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Additional required properties for imx8 pcie:
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- hsio-cfg: hsio configration mode when the pcie node is supported.
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mode 1: pciea 2 lanes and one sata ahci port.
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mode 2: pciea 1 lane, pcieb 1 lane and one sata ahci port.
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mode 3: pciea 2 lanes, pcieb 1 lane.
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- local-addr: the local address used in hsio module.
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Example:
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hsio-cfg = <PCIEAX2PCIEBX1>;
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hsio = <&hsio>;
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local-addr = <0x80000000>;
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Example:
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pcie@01000000 {
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compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
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reg = <0x01ffc000 0x04000>,
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<0x01f00000 0x80000>;
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reg-names = "dbi", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
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0x81000000 0 0 0x01f80000 0 0x00010000
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0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
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num-lanes = <1>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks 144>, <&clks 206>, <&clks 189>;
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clock-names = "pcie", "pcie_bus", "pcie_phy";
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};
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* Freescale i.MX7d PCIe PHY
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This is the PHY associated with the IMX7d PCIe controller. It's used by the
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PCI-e controller via the fsl,imx7d-pcie-phy phandle.
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Required properties:
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- compatible:
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- "fsl,imx7d-pcie-phy"
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- reg: base address and length of the PCIe PHY controller
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