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This is the 5.4.135 stable release 

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Merge tag 'v5.4.135' into 5.4-2.3.x-imx

This is the 5.4.135 stable release

Conflicts (manual resolve):
- drivers/usb/cdns3/gadget.c:
Use NXP version, as upstream commit f53729b828 ("usb: cdns3: Enable
TDL_CHK only for OUT ep") is already applied.

- arch/arm64/boot/dts/freescale/imx8mq.dtsi:
Merge upstream commit 556cf02830 ("arm64: dts: imx8mq: assign PCIe
clocks") manually into NXP tree.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
This commit is contained in:
Andrey Zhizhikin 2021-08-04 14:25:42 +00:00
parent e3b082933c 0a0beb1f91
commit 90c98361bb
104 changed files with 445 additions and 221 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0
VERSION = 5 VERSION = 5
PATCHLEVEL = 4 PATCHLEVEL = 4
SUBLEVEL = 134 SUBLEVEL = 135
EXTRAVERSION = EXTRAVERSION =
NAME = Kleptomaniac Octopus NAME = Kleptomaniac Octopus

5
arch/arm/boot/dts/am437x-gp-evm.dts
View File

@ -829,11 +829,14 @@
status = "okay"; status = "okay";
}; };
&gpio5_target {
ti,no-reset-on-init;
};
&gpio5 { &gpio5 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&display_mux_pins>; pinctrl-0 = <&display_mux_pins>;
status = "okay"; status = "okay";
ti,no-reset-on-init;
p8 { p8 {
/* /*

2
arch/arm/boot/dts/am437x-l4.dtsi
View File

@ -2077,7 +2077,7 @@
}; };
}; };
target-module@22000 { /* 0x48322000, ap 116 64.0 */ gpio5_target: target-module@22000 { /* 0x48322000, ap 116 64.0 */
compatible = "ti,sysc-omap2", "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio6"; ti,hwmods = "gpio6";
reg = <0x22000 0x4>, reg = <0x22000 0x4>,

5
arch/arm/boot/dts/am57xx-cl-som-am57x.dts
View File

@ -611,12 +611,11 @@
>; >;
}; };
&gpio3 { &gpio3_target {
status = "okay";
ti,no-reset-on-init; ti,no-reset-on-init;
}; };
&gpio2 { &gpio2_target {
status = "okay"; status = "okay";
ti,no-reset-on-init; ti,no-reset-on-init;
}; };

2
arch/arm/boot/dts/bcm-cygnus.dtsi
View File

@ -460,7 +460,7 @@
status = "disabled"; status = "disabled";
}; };
nand: nand@18046000 { nand_controller: nand-controller@18046000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x18046000 0x600>, <0xf8105408 0x600>, reg = <0x18046000 0x600>, <0xf8105408 0x600>,
<0x18046f00 0x20>; <0x18046f00 0x20>;

2
arch/arm/boot/dts/bcm-hr2.dtsi
View File

@ -179,7 +179,7 @@
status = "disabled"; status = "disabled";
}; };
nand: nand@26000 { nand_controller: nand-controller@26000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x26000 0x600>, reg = <0x26000 0x600>,
<0x11b408 0x600>, <0x11b408 0x600>,

2
arch/arm/boot/dts/bcm-nsp.dtsi
View File

@ -267,7 +267,7 @@
dma-coherent; dma-coherent;
}; };
nand: nand@26000 { nand_controller: nand-controller@26000 {
compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
reg = <0x026000 0x600>, reg = <0x026000 0x600>,
<0x11b408 0x600>, <0x11b408 0x600>,

2
arch/arm/boot/dts/bcm63138.dtsi
View File

@ -203,7 +203,7 @@
status = "disabled"; status = "disabled";
}; };
nand: nand@2000 { nand_controller: nand-controller@2000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand"; compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";

4
arch/arm/boot/dts/bcm7445-bcm97445svmb.dts
View File

@ -14,10 +14,10 @@
}; };
}; };
&nand { &nand_controller {
status = "okay"; status = "okay";
nandcs@1 { nand@1 {
compatible = "brcm,nandcs"; compatible = "brcm,nandcs";
reg = <1>; reg = <1>;
nand-ecc-step-size = <512>; nand-ecc-step-size = <512>;

2
arch/arm/boot/dts/bcm7445.dtsi
View File

@ -148,7 +148,7 @@
reg-names = "aon-ctrl", "aon-sram"; reg-names = "aon-ctrl", "aon-sram";
}; };
nand: nand@3e2800 { nand_controller: nand-controller@3e2800 {
status = "disabled"; status = "disabled";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;

4
arch/arm/boot/dts/bcm911360_entphn.dts
View File

@ -82,8 +82,8 @@
status = "okay"; status = "okay";
}; };
&nand { &nand_controller {
nandcs@1 { nand@1 {
compatible = "brcm,nandcs"; compatible = "brcm,nandcs";
reg = <0>; reg = <0>;
nand-on-flash-bbt; nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958300k.dts
View File

@ -60,8 +60,8 @@
status = "okay"; status = "okay";
}; };
&nand { &nand_controller {
nandcs@1 { nand@1 {
compatible = "brcm,nandcs"; compatible = "brcm,nandcs";
reg = <0>; reg = <0>;
nand-on-flash-bbt; nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958305k.dts
View File

@ -68,8 +68,8 @@
status = "okay"; status = "okay";
}; };
&nand { &nand_controller {
nandcs@1 { nand@1 {
compatible = "brcm,nandcs"; compatible = "brcm,nandcs";
reg = <0>; reg = <0>;
nand-on-flash-bbt; nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958522er.dts
View File

@ -70,8 +70,8 @@
status = "okay"; status = "okay";
}; };
&nand { &nand_controller {
nandcs@0 { nand@0 {
compatible = "brcm,nandcs"; compatible = "brcm,nandcs";
reg = <0>; reg = <0>;
nand-on-flash-bbt; nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958525er.dts
View File

@ -70,8 +70,8 @@
status = "okay"; status = "okay";
}; };
&nand { &nand_controller {
nandcs@0 { nand@0 {
compatible = "brcm,nandcs"; compatible = "brcm,nandcs";
reg = <0>; reg = <0>;
nand-on-flash-bbt; nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958525xmc.dts
View File

@ -86,8 +86,8 @@
}; };
}; };
&nand { &nand_controller {
nandcs@0 { nand@0 {
compatible = "brcm,nandcs"; compatible = "brcm,nandcs";
reg = <0>; reg = <0>;
nand-on-flash-bbt; nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958622hr.dts
View File

@ -74,8 +74,8 @@
status = "okay"; status = "okay";
}; };
&nand { &nand_controller {
nandcs@0 { nand@0 {
compatible = "brcm,nandcs"; compatible = "brcm,nandcs";
reg = <0>; reg = <0>;
nand-on-flash-bbt; nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958623hr.dts
View File

@ -74,8 +74,8 @@
status = "okay"; status = "okay";
}; };
&nand { &nand_controller {
nandcs@0 { nand@0 {
compatible = "brcm,nandcs"; compatible = "brcm,nandcs";
reg = <0>; reg = <0>;
nand-on-flash-bbt; nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958625hr.dts
View File

@ -90,8 +90,8 @@
status = "okay"; status = "okay";
}; };
&nand { &nand_controller {
nandcs@0 { nand@0 {
compatible = "brcm,nandcs"; compatible = "brcm,nandcs";
reg = <0>; reg = <0>;
nand-on-flash-bbt; nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm958625k.dts
View File

@ -64,8 +64,8 @@
status = "okay"; status = "okay";
}; };
&nand { &nand_controller {
nandcs@0 { nand@0 {
compatible = "brcm,nandcs"; compatible = "brcm,nandcs";
reg = <0>; reg = <0>;
nand-on-flash-bbt; nand-on-flash-bbt;

4
arch/arm/boot/dts/bcm963138dvt.dts
View File

@ -31,10 +31,10 @@
status = "okay"; status = "okay";
}; };
&nand { &nand_controller {
status = "okay"; status = "okay";
nandcs@0 { nand@0 {
compatible = "brcm,nandcs"; compatible = "brcm,nandcs";
reg = <0>; reg = <0>;
nand-ecc-strength = <4>; nand-ecc-strength = <4>;

4
arch/arm/boot/dts/bcm988312hr.dts
View File

@ -74,8 +74,8 @@
status = "okay"; status = "okay";
}; };
&nand { &nand_controller {
nandcs@0 { nand@0 {
compatible = "brcm,nandcs"; compatible = "brcm,nandcs";
reg = <0>; reg = <0>;
nand-on-flash-bbt; nand-on-flash-bbt;

4
arch/arm/boot/dts/dra7-l4.dtsi
View File

@ -1326,7 +1326,7 @@
}; };
}; };
target-module@55000 { /* 0x48055000, ap 13 0e.0 */ gpio2_target: target-module@55000 { /* 0x48055000, ap 13 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x55000 0x4>, reg = <0x55000 0x4>,
<0x55010 0x4>, <0x55010 0x4>,
@ -1359,7 +1359,7 @@
}; };
}; };
target-module@57000 { /* 0x48057000, ap 15 06.0 */ gpio3_target: target-module@57000 { /* 0x48057000, ap 15 06.0 */
compatible = "ti,sysc-omap2", "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x57000 0x4>, reg = <0x57000 0x4>,
<0x57010 0x4>, <0x57010 0x4>,

2
arch/arm/boot/dts/gemini-dlink-dns-313.dts
View File

@ -140,7 +140,7 @@
}; };
}; };
mdio0: ethernet-phy { mdio0: mdio {
compatible = "virtual,mdio-gpio"; compatible = "virtual,mdio-gpio";
/* Uses MDC and MDIO */ /* Uses MDC and MDIO */
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */

2
arch/arm/boot/dts/gemini-nas4220b.dts
View File

@ -62,7 +62,7 @@
}; };
}; };
mdio0: ethernet-phy { mdio0: mdio {
compatible = "virtual,mdio-gpio"; compatible = "virtual,mdio-gpio";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */

2
arch/arm/boot/dts/gemini-rut1xx.dts
View File

@ -56,7 +56,7 @@
}; };
}; };
mdio0: ethernet-phy { mdio0: mdio {
compatible = "virtual,mdio-gpio"; compatible = "virtual,mdio-gpio";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */

2
arch/arm/boot/dts/gemini-wbd111.dts
View File

@ -68,7 +68,7 @@
}; };
}; };
mdio0: ethernet-phy { mdio0: mdio {
compatible = "virtual,mdio-gpio"; compatible = "virtual,mdio-gpio";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */

2
arch/arm/boot/dts/gemini-wbd222.dts
View File

@ -67,7 +67,7 @@
}; };
}; };
mdio0: ethernet-phy { mdio0: mdio {
compatible = "virtual,mdio-gpio"; compatible = "virtual,mdio-gpio";
gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>, /* MDC */
<&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */ <&gpio0 21 GPIO_ACTIVE_HIGH>; /* MDIO */

1
arch/arm/boot/dts/gemini.dtsi
View File

@ -286,6 +286,7 @@
clock-names = "PCLK", "PCICLK"; clock-names = "PCLK", "PCICLK";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pci_default_pins>; pinctrl-0 = <&pci_default_pins>;
device_type = "pci";
#address-cells = <3>; #address-cells = <3>;
#size-cells = <2>; #size-cells = <2>;
#interrupt-cells = <1>; #interrupt-cells = <1>;

5
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
View File

@ -315,8 +315,8 @@
fsl,pins = < fsl,pins = <
MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
>; >;
}; };
@ -403,6 +403,7 @@
&uart3 { &uart3 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>; pinctrl-0 = <&pinctrl_uart3>;
uart-has-rtscts;
status = "disabled"; status = "disabled";
}; };

2
arch/arm/boot/dts/rk3036-kylin.dts
View File

@ -390,7 +390,7 @@
}; };
}; };
sleep { suspend {
global_pwroff: global-pwroff { global_pwroff: global-pwroff {
rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>;
}; };

6
arch/arm/boot/dts/rk3066a.dtsi
View File

@ -761,7 +761,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pd_vio@RK3066_PD_VIO { power-domain@RK3066_PD_VIO {
reg = <RK3066_PD_VIO>; reg = <RK3066_PD_VIO>;
clocks = <&cru ACLK_LCDC0>, clocks = <&cru ACLK_LCDC0>,
<&cru ACLK_LCDC1>, <&cru ACLK_LCDC1>,
@ -788,7 +788,7 @@
<&qos_rga>; <&qos_rga>;
}; };
pd_video@RK3066_PD_VIDEO { power-domain@RK3066_PD_VIDEO {
reg = <RK3066_PD_VIDEO>; reg = <RK3066_PD_VIDEO>;
clocks = <&cru ACLK_VDPU>, clocks = <&cru ACLK_VDPU>,
<&cru ACLK_VEPU>, <&cru ACLK_VEPU>,
@ -797,7 +797,7 @@
pm_qos = <&qos_vpu>; pm_qos = <&qos_vpu>;
}; };
pd_gpu@RK3066_PD_GPU { power-domain@RK3066_PD_GPU {
reg = <RK3066_PD_GPU>; reg = <RK3066_PD_GPU>;
clocks = <&cru ACLK_GPU>; clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>; pm_qos = <&qos_gpu>;

14
arch/arm/boot/dts/rk3188.dtsi
View File

@ -150,16 +150,16 @@
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x2000e000 0x20>; reg = <0x2000e000 0x20>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>; clocks = <&cru PCLK_TIMER3>, <&cru SCLK_TIMER3>;
clock-names = "timer", "pclk"; clock-names = "pclk", "timer";
}; };
timer6: timer@200380a0 { timer6: timer@200380a0 {
compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer"; compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
reg = <0x200380a0 0x20>; reg = <0x200380a0 0x20>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>; clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER6>;
clock-names = "timer", "pclk"; clock-names = "pclk", "timer";
}; };
i2s0: i2s@1011a000 { i2s0: i2s@1011a000 {
@ -701,7 +701,7 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pd_vio@RK3188_PD_VIO { power-domain@RK3188_PD_VIO {
reg = <RK3188_PD_VIO>; reg = <RK3188_PD_VIO>;
clocks = <&cru ACLK_LCDC0>, clocks = <&cru ACLK_LCDC0>,
<&cru ACLK_LCDC1>, <&cru ACLK_LCDC1>,
@ -723,7 +723,7 @@
<&qos_rga>; <&qos_rga>;
}; };
pd_video@RK3188_PD_VIDEO { power-domain@RK3188_PD_VIDEO {
reg = <RK3188_PD_VIDEO>; reg = <RK3188_PD_VIDEO>;
clocks = <&cru ACLK_VDPU>, clocks = <&cru ACLK_VDPU>,
<&cru ACLK_VEPU>, <&cru ACLK_VEPU>,
@ -732,7 +732,7 @@
pm_qos = <&qos_vpu>; pm_qos = <&qos_vpu>;
}; };
pd_gpu@RK3188_PD_GPU { power-domain@RK3188_PD_GPU {
reg = <RK3188_PD_GPU>; reg = <RK3188_PD_GPU>;
clocks = <&cru ACLK_GPU>; clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>; pm_qos = <&qos_gpu>;

10
arch/arm/boot/dts/rk322x.dtsi
View File

@ -570,10 +570,9 @@
compatible = "rockchip,iommu"; compatible = "rockchip,iommu";
reg = <0x20020800 0x100>; reg = <0x20020800 0x100>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
clock-names = "aclk", "iface"; clock-names = "aclk", "iface";
iommu-cells = <0>; #iommu-cells = <0>;
status = "disabled"; status = "disabled";
}; };
@ -581,10 +580,9 @@
compatible = "rockchip,iommu"; compatible = "rockchip,iommu";
reg = <0x20030480 0x40>, <0x200304c0 0x40>; reg = <0x20030480 0x40>, <0x200304c0 0x40>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vdec_mmu";
clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
clock-names = "aclk", "iface"; clock-names = "aclk", "iface";
iommu-cells = <0>; #iommu-cells = <0>;
status = "disabled"; status = "disabled";
}; };
@ -614,7 +612,6 @@
compatible = "rockchip,iommu"; compatible = "rockchip,iommu";
reg = <0x20053f00 0x100>; reg = <0x20053f00 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
clock-names = "aclk", "iface"; clock-names = "aclk", "iface";
#iommu-cells = <0>; #iommu-cells = <0>;
@ -625,10 +622,9 @@
compatible = "rockchip,iommu"; compatible = "rockchip,iommu";
reg = <0x20070800 0x100>; reg = <0x20070800 0x100>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "iep_mmu";
clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
clock-names = "aclk", "iface"; clock-names = "aclk", "iface";
iommu-cells = <0>; #iommu-cells = <0>;
status = "disabled"; status = "disabled";
}; };

2
arch/arm/boot/dts/rk3288-rock2-som.dtsi
View File

@ -218,7 +218,7 @@
flash0-supply = <&vcc_flash>; flash0-supply = <&vcc_flash>;
flash1-supply = <&vccio_pmu>; flash1-supply = <&vccio_pmu>;
gpio30-supply = <&vccio_pmu>; gpio30-supply = <&vccio_pmu>;
gpio1830 = <&vcc_io>; gpio1830-supply = <&vcc_io>;
lcdc-supply = <&vcc_io>; lcdc-supply = <&vcc_io>;
sdcard-supply = <&vccio_sd>; sdcard-supply = <&vccio_sd>;
wifi-supply = <&vcc_18>; wifi-supply = <&vcc_18>;

4
arch/arm/boot/dts/rk3288-vyasa.dts
View File

@ -357,10 +357,10 @@
audio-supply = <&vcc_18>; audio-supply = <&vcc_18>;
bb-supply = <&vcc_io>; bb-supply = <&vcc_io>;
dvp-supply = <&vcc_io>; dvp-supply = <&vcc_io>;
flash0-suuply = <&vcc_18>; flash0-supply = <&vcc_18>;
flash1-supply = <&vcc_lan>; flash1-supply = <&vcc_lan>;
gpio30-supply = <&vcc_io>; gpio30-supply = <&vcc_io>;
gpio1830 = <&vcc_io>; gpio1830-supply = <&vcc_io>;
lcdc-supply = <&vcc_io>; lcdc-supply = <&vcc_io>;
sdcard-supply = <&vccio_sd>; sdcard-supply = <&vccio_sd>;
wifi-supply = <&vcc_18>; wifi-supply = <&vcc_18>;

14
arch/arm/boot/dts/rk3288.dtsi
View File

@ -238,8 +238,8 @@
compatible = "rockchip,rk3288-timer"; compatible = "rockchip,rk3288-timer";
reg = <0x0 0xff810000 0x0 0x20>; reg = <0x0 0xff810000 0x0 0x20>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xin24m>, <&cru PCLK_TIMER>; clocks = <&cru PCLK_TIMER>, <&xin24m>;
clock-names = "timer", "pclk"; clock-names = "pclk", "timer";
}; };
display-subsystem { display-subsystem {
@ -771,7 +771,7 @@
* *_HDMI HDMI * *_HDMI HDMI
* *_MIPI_* MIPI * *_MIPI_* MIPI
*/ */
pd_vio@RK3288_PD_VIO { power-domain@RK3288_PD_VIO {
reg = <RK3288_PD_VIO>; reg = <RK3288_PD_VIO>;
clocks = <&cru ACLK_IEP>, clocks = <&cru ACLK_IEP>,
<&cru ACLK_ISP>, <&cru ACLK_ISP>,
@ -813,7 +813,7 @@
* Note: The following 3 are HEVC(H.265) clocks, * Note: The following 3 are HEVC(H.265) clocks,
* and on the ACLK_HEVC_NIU (NOC). * and on the ACLK_HEVC_NIU (NOC).
*/ */
pd_hevc@RK3288_PD_HEVC { power-domain@RK3288_PD_HEVC {
reg = <RK3288_PD_HEVC>; reg = <RK3288_PD_HEVC>;
clocks = <&cru ACLK_HEVC>, clocks = <&cru ACLK_HEVC>,
<&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CABAC>,
@ -827,7 +827,7 @@
* (video endecoder & decoder) clocks that on the * (video endecoder & decoder) clocks that on the
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
*/ */
pd_video@RK3288_PD_VIDEO { power-domain@RK3288_PD_VIDEO {
reg = <RK3288_PD_VIDEO>; reg = <RK3288_PD_VIDEO>;
clocks = <&cru ACLK_VCODEC>, clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>; <&cru HCLK_VCODEC>;
@ -838,7 +838,7 @@
* Note: ACLK_GPU is the GPU clock, * Note: ACLK_GPU is the GPU clock,
* and on the ACLK_GPU_NIU (NOC). * and on the ACLK_GPU_NIU (NOC).
*/ */
pd_gpu@RK3288_PD_GPU { power-domain@RK3288_PD_GPU {
reg = <RK3288_PD_GPU>; reg = <RK3288_PD_GPU>;
clocks = <&cru ACLK_GPU>; clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu_r>, pm_qos = <&qos_gpu_r>,
@ -1575,7 +1575,7 @@
drive-strength = <12>; drive-strength = <12>;
}; };
sleep { suspend {
global_pwroff: global-pwroff { global_pwroff: global-pwroff {
rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>; rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>;
}; };

8
arch/arm/boot/dts/stm32429i-eval.dts
View File

@ -112,17 +112,15 @@
}; };
}; };
gpio_keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat; autorepeat;
button@0 { button-0 {
label = "Wake up"; label = "Wake up";
linux,code = <KEY_WAKEUP>; linux,code = <KEY_WAKEUP>;
gpios = <&gpioa 0 0>; gpios = <&gpioa 0 0>;
}; };
button@1 { button-1 {
label = "Tamper"; label = "Tamper";
linux,code = <KEY_RESTART>; linux,code = <KEY_RESTART>;
gpios = <&gpioc 13 0>; gpios = <&gpioc 13 0>;

6
arch/arm/boot/dts/stm32746g-eval.dts
View File

@ -81,12 +81,10 @@
}; };
}; };
gpio_keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat; autorepeat;
button@0 { button-0 {
label = "Wake up"; label = "Wake up";
linux,code = <KEY_WAKEUP>; linux,code = <KEY_WAKEUP>;
gpios = <&gpioc 13 0>; gpios = <&gpioc 13 0>;

6
arch/arm/boot/dts/stm32f429-disco.dts
View File

@ -79,12 +79,10 @@
}; };
}; };
gpio_keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat; autorepeat;
button@0 { button-0 {
label = "User"; label = "User";
linux,code = <KEY_HOME>; linux,code = <KEY_HOME>;
gpios = <&gpioa 0 0>; gpios = <&gpioa 0 0>;

10
arch/arm/boot/dts/stm32f429.dtsi
View File

@ -283,8 +283,6 @@
}; };
timers13: timers@40001c00 { timers13: timers@40001c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>; reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
@ -299,8 +297,6 @@
}; };
timers14: timers@40002000 { timers14: timers@40002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40002000 0x400>; reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>; clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
@ -623,8 +619,6 @@
}; };
timers10: timers@40014400 { timers10: timers@40014400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40014400 0x400>; reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
@ -639,8 +633,6 @@
}; };
timers11: timers@40014800 { timers11: timers@40014800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40014800 0x400>; reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>; clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
@ -696,7 +688,7 @@
status = "disabled"; status = "disabled";
}; };
rcc: rcc@40023810 { rcc: rcc@40023800 {
#reset-cells = <1>; #reset-cells = <1>;
#clock-cells = <2>; #clock-cells = <2>;
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";

6
arch/arm/boot/dts/stm32f469-disco.dts
View File

@ -104,12 +104,10 @@
}; };
}; };
gpio_keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat; autorepeat;
button@0 { button-0 {
label = "User"; label = "User";
linux,code = <KEY_WAKEUP>; linux,code = <KEY_WAKEUP>;
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;

12
arch/arm/boot/dts/stm32f746.dtsi
View File

@ -265,8 +265,6 @@
}; };
timers13: timers@40001c00 { timers13: timers@40001c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40001C00 0x400>; reg = <0x40001C00 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
@ -281,8 +279,6 @@
}; };
timers14: timers@40002000 { timers14: timers@40002000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40002000 0x400>; reg = <0x40002000 0x400>;
clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>; clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
@ -366,9 +362,9 @@
status = "disabled"; status = "disabled";
}; };
i2c3: i2c@40005C00 { i2c3: i2c@40005c00 {
compatible = "st,stm32f7-i2c"; compatible = "st,stm32f7-i2c";
reg = <0x40005C00 0x400>; reg = <0x40005c00 0x400>;
interrupts = <72>, interrupts = <72>,
<73>; <73>;
resets = <&rcc STM32F7_APB1_RESET(I2C3)>; resets = <&rcc STM32F7_APB1_RESET(I2C3)>;
@ -533,8 +529,6 @@
}; };
timers10: timers@40014400 { timers10: timers@40014400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40014400 0x400>; reg = <0x40014400 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM10)>;
@ -549,8 +543,6 @@
}; };
timers11: timers@40014800 { timers11: timers@40014800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-timers"; compatible = "st,stm32-timers";
reg = <0x40014800 0x400>; reg = <0x40014800 0x400>;
clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>; clocks = <&rcc 0 STM32F7_APB2_CLOCK(TIM11)>;

6
arch/arm/boot/dts/stm32f769-disco.dts
View File

@ -75,12 +75,10 @@
}; };
}; };
gpio_keys { gpio-keys {
compatible = "gpio-keys"; compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat; autorepeat;
button@0 { button-0 {
label = "User"; label = "User";
linux,code = <KEY_HOME>; linux,code = <KEY_HOME>;
gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>; gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;

4
arch/arm/boot/dts/stm32h743.dtsi
View File

@ -438,8 +438,6 @@
}; };
lptimer4: timer@58002c00 { lptimer4: timer@58002c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer"; compatible = "st,stm32-lptimer";
reg = <0x58002c00 0x400>; reg = <0x58002c00 0x400>;
clocks = <&rcc LPTIM4_CK>; clocks = <&rcc LPTIM4_CK>;
@ -454,8 +452,6 @@
}; };
lptimer5: timer@58003000 { lptimer5: timer@58003000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "st,stm32-lptimer"; compatible = "st,stm32-lptimer";
reg = <0x58003000 0x400>; reg = <0x58003000 0x400>;
clocks = <&rcc LPTIM5_CK>; clocks = <&rcc LPTIM5_CK>;

12
arch/arm/boot/dts/stm32mp157c.dtsi
View File

@ -1311,12 +1311,6 @@
status = "disabled"; status = "disabled";
}; };
stmmac_axi_config_0: stmmac-axi-config {
snps,wr_osr_lmt = <0x7>;
snps,rd_osr_lmt = <0x7>;
snps,blen = <0 0 0 0 16 8 4>;
};
ethernet0: ethernet@5800a000 { ethernet0: ethernet@5800a000 {
compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
reg = <0x5800a000 0x2000>; reg = <0x5800a000 0x2000>;
@ -1339,6 +1333,12 @@
snps,axi-config = <&stmmac_axi_config_0>; snps,axi-config = <&stmmac_axi_config_0>;
snps,tso; snps,tso;
status = "disabled"; status = "disabled";
stmmac_axi_config_0: stmmac-axi-config {
snps,wr_osr_lmt = <0x7>;
snps,rd_osr_lmt = <0x7>;
snps,blen = <0 0 0 0 16 8 4>;
};
}; };
usbh_ohci: usbh-ohci@5800c000 { usbh_ohci: usbh-ohci@5800c000 {

4
arch/arm/mach-imx/suspend-imx53.S
View File

@ -28,11 +28,11 @@
* ^ * ^
* ^ * ^
* imx53_suspend code * imx53_suspend code
* PM_INFO structure(imx53_suspend_info) * PM_INFO structure(imx5_cpu_suspend_info)
* ======================== low address ======================= * ======================== low address =======================
*/ */
/* Offsets of members of struct imx53_suspend_info */ /* Offsets of members of struct imx5_cpu_suspend_info */
#define SUSPEND_INFO_MX53_M4IF_V_OFFSET 0x0 #define SUSPEND_INFO_MX53_M4IF_V_OFFSET 0x0
#define SUSPEND_INFO_MX53_IOMUXC_V_OFFSET 0x4 #define SUSPEND_INFO_MX53_IOMUXC_V_OFFSET 0x4
#define SUSPEND_INFO_MX53_IO_COUNT_OFFSET 0x8 #define SUSPEND_INFO_MX53_IO_COUNT_OFFSET 0x8

6
arch/arm64/boot/dts/arm/juno-base.dtsi
View File

@ -537,13 +537,13 @@
clocks { clocks {
compatible = "arm,scpi-clocks"; compatible = "arm,scpi-clocks";
scpi_dvfs: scpi-dvfs { scpi_dvfs: clocks-0 {
compatible = "arm,scpi-dvfs-clocks"; compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = <0>, <1>, <2>; clock-indices = <0>, <1>, <2>;
clock-output-names = "atlclk", "aplclk","gpuclk"; clock-output-names = "atlclk", "aplclk","gpuclk";
}; };
scpi_clk: scpi-clk { scpi_clk: clocks-1 {
compatible = "arm,scpi-variable-clocks"; compatible = "arm,scpi-variable-clocks";
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = <3>; clock-indices = <3>;
@ -551,7 +551,7 @@
}; };
}; };
scpi_devpd: scpi-power-domains { scpi_devpd: power-controller {
compatible = "arm,scpi-power-domains"; compatible = "arm,scpi-power-domains";
num-domains = <2>; num-domains = <2>;
#power-domain-cells = <1>; #power-domain-cells = <1>;

1
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@ -466,7 +466,6 @@
clocks = <&clockgen 4 3>; clocks = <&clockgen 4 3>;
clock-names = "dspi"; clock-names = "dspi";
spi-num-chipselects = <5>; spi-num-chipselects = <5>;
bus-num = <0>;
}; };
esdhc: esdhc@2140000 { esdhc: esdhc@2140000 {

16
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -1446,6 +1446,14 @@
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>,
<&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "clkreq", "turnoff"; reset-names = "pciephy", "apps", "clkreq", "turnoff";
assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&clk IMX8MQ_CLK_PCIE1_AUX>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
<&clk IMX8MQ_SYS2_PLL_100M>,
<&clk IMX8MQ_SYS1_PLL_80M>;
assigned-clock-rates = <250000000>, <100000000>,
<10000000>;
status = "disabled"; status = "disabled";
}; };
@ -1494,6 +1502,14 @@
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
<&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
reset-names = "pciephy", "apps", "turnoff"; reset-names = "pciephy", "apps", "turnoff";
assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&clk IMX8MQ_CLK_PCIE2_AUX>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
<&clk IMX8MQ_SYS2_PLL_100M>,
<&clk IMX8MQ_SYS1_PLL_80M>;
assigned-clock-rates = <250000000>, <100000000>,
<10000000>;
num-ib-windows = <4>; num-ib-windows = <4>;
num-ob-windows = <4>; num-ob-windows = <4>;
status = "disabled"; status = "disabled";

6
arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
View File

@ -106,6 +106,12 @@
/* enabled by U-Boot if SFP module is present */ /* enabled by U-Boot if SFP module is present */
status = "disabled"; status = "disabled";
}; };
firmware {
armada-3700-rwtm {
compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm";
};
};
}; };
&i2c0 { &i2c0 {

8
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View File

@ -500,4 +500,12 @@
}; };
}; };
}; };
firmware {
armada-3700-rwtm {
compatible = "marvell,armada-3700-rwtm-firmware";
mboxes = <&rwtm 0>;
status = "okay";
};
};
}; };

16
arch/arm64/boot/dts/rockchip/px30.dtsi
View File

@ -213,20 +213,20 @@
#size-cells = <0>; #size-cells = <0>;
/* These power domains are grouped by VD_LOGIC */ /* These power domains are grouped by VD_LOGIC */
pd_usb@PX30_PD_USB { power-domain@PX30_PD_USB {
reg = <PX30_PD_USB>; reg = <PX30_PD_USB>;
clocks = <&cru HCLK_HOST>, clocks = <&cru HCLK_HOST>,
<&cru HCLK_OTG>, <&cru HCLK_OTG>,
<&cru SCLK_OTG_ADP>; <&cru SCLK_OTG_ADP>;
pm_qos = <&qos_usb_host>, <&qos_usb_otg>; pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
}; };
pd_sdcard@PX30_PD_SDCARD { power-domain@PX30_PD_SDCARD {
reg = <PX30_PD_SDCARD>; reg = <PX30_PD_SDCARD>;
clocks = <&cru HCLK_SDMMC>, clocks = <&cru HCLK_SDMMC>,
<&cru SCLK_SDMMC>; <&cru SCLK_SDMMC>;
pm_qos = <&qos_sdmmc>; pm_qos = <&qos_sdmmc>;
}; };
pd_gmac@PX30_PD_GMAC { power-domain@PX30_PD_GMAC {
reg = <PX30_PD_GMAC>; reg = <PX30_PD_GMAC>;
clocks = <&cru ACLK_GMAC>, clocks = <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>, <&cru PCLK_GMAC>,
@ -234,7 +234,7 @@
<&cru SCLK_GMAC_RX_TX>; <&cru SCLK_GMAC_RX_TX>;
pm_qos = <&qos_gmac>; pm_qos = <&qos_gmac>;
}; };
pd_mmc_nand@PX30_PD_MMC_NAND { power-domain@PX30_PD_MMC_NAND {
reg = <PX30_PD_MMC_NAND>; reg = <PX30_PD_MMC_NAND>;
clocks = <&cru HCLK_NANDC>, clocks = <&cru HCLK_NANDC>,
<&cru HCLK_EMMC>, <&cru HCLK_EMMC>,
@ -247,14 +247,14 @@
pm_qos = <&qos_emmc>, <&qos_nand>, pm_qos = <&qos_emmc>, <&qos_nand>,
<&qos_sdio>, <&qos_sfc>; <&qos_sdio>, <&qos_sfc>;
}; };
pd_vpu@PX30_PD_VPU { power-domain@PX30_PD_VPU {
reg = <PX30_PD_VPU>; reg = <PX30_PD_VPU>;
clocks = <&cru ACLK_VPU>, clocks = <&cru ACLK_VPU>,
<&cru HCLK_VPU>, <&cru HCLK_VPU>,
<&cru SCLK_CORE_VPU>; <&cru SCLK_CORE_VPU>;
pm_qos = <&qos_vpu>, <&qos_vpu_r128>; pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
}; };
pd_vo@PX30_PD_VO { power-domain@PX30_PD_VO {
reg = <PX30_PD_VO>; reg = <PX30_PD_VO>;
clocks = <&cru ACLK_RGA>, clocks = <&cru ACLK_RGA>,
<&cru ACLK_VOPB>, <&cru ACLK_VOPB>,
@ -270,7 +270,7 @@
pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
<&qos_vop_m0>, <&qos_vop_m1>; <&qos_vop_m0>, <&qos_vop_m1>;
}; };
pd_vi@PX30_PD_VI { power-domain@PX30_PD_VI {
reg = <PX30_PD_VI>; reg = <PX30_PD_VI>;
clocks = <&cru ACLK_CIF>, clocks = <&cru ACLK_CIF>,
<&cru ACLK_ISP>, <&cru ACLK_ISP>,
@ -281,7 +281,7 @@
<&qos_isp_wr>, <&qos_isp_m1>, <&qos_isp_wr>, <&qos_isp_m1>,
<&qos_vip>; <&qos_vip>;
}; };
pd_gpu@PX30_PD_GPU { power-domain@PX30_PD_GPU {
reg = <PX30_PD_GPU>; reg = <PX30_PD_GPU>;
clocks = <&cru SCLK_GPU>; clocks = <&cru SCLK_GPU>;
pm_qos = <&qos_gpu>; pm_qos = <&qos_gpu>;

6
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@ -270,13 +270,13 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pd_hevc@RK3328_PD_HEVC { power-domain@RK3328_PD_HEVC {
reg = <RK3328_PD_HEVC>; reg = <RK3328_PD_HEVC>;
}; };
pd_video@RK3328_PD_VIDEO { power-domain@RK3328_PD_VIDEO {
reg = <RK3328_PD_VIDEO>; reg = <RK3328_PD_VIDEO>;
}; };
pd_vpu@RK3328_PD_VPU { power-domain@RK3328_PD_VPU {
reg = <RK3328_PD_VPU>; reg = <RK3328_PD_VPU>;
clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
}; };

2
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@ -2317,7 +2317,7 @@
}; };
}; };
sleep { suspend {
ap_pwroff: ap-pwroff { ap_pwroff: ap-pwroff {
rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
}; };

97
arch/s390/include/asm/stacktrace.h
View File

@ -115,6 +115,103 @@ struct stack_frame {
r2; \ r2; \
}) })
#define CALL_LARGS_0(...) \
long dummy = 0
#define CALL_LARGS_1(t1, a1) \
long arg1 = (long)(t1)(a1)
#define CALL_LARGS_2(t1, a1, t2, a2) \
CALL_LARGS_1(t1, a1); \
long arg2 = (long)(t2)(a2)
#define CALL_LARGS_3(t1, a1, t2, a2, t3, a3) \
CALL_LARGS_2(t1, a1, t2, a2); \
long arg3 = (long)(t3)(a3)
#define CALL_LARGS_4(t1, a1, t2, a2, t3, a3, t4, a4) \
CALL_LARGS_3(t1, a1, t2, a2, t3, a3); \
long arg4 = (long)(t4)(a4)
#define CALL_LARGS_5(t1, a1, t2, a2, t3, a3, t4, a4, t5, a5) \
CALL_LARGS_4(t1, a1, t2, a2, t3, a3, t4, a4); \
long arg5 = (long)(t5)(a5)
#define CALL_REGS_0 \
register long r2 asm("2") = dummy
#define CALL_REGS_1 \
register long r2 asm("2") = arg1
#define CALL_REGS_2 \
CALL_REGS_1; \
register long r3 asm("3") = arg2
#define CALL_REGS_3 \
CALL_REGS_2; \
register long r4 asm("4") = arg3
#define CALL_REGS_4 \
CALL_REGS_3; \
register long r5 asm("5") = arg4
#define CALL_REGS_5 \
CALL_REGS_4; \
register long r6 asm("6") = arg5
#define CALL_TYPECHECK_0(...)
#define CALL_TYPECHECK_1(t, a, ...) \
typecheck(t, a)
#define CALL_TYPECHECK_2(t, a, ...) \
CALL_TYPECHECK_1(__VA_ARGS__); \
typecheck(t, a)
#define CALL_TYPECHECK_3(t, a, ...) \
CALL_TYPECHECK_2(__VA_ARGS__); \
typecheck(t, a)
#define CALL_TYPECHECK_4(t, a, ...) \
CALL_TYPECHECK_3(__VA_ARGS__); \
typecheck(t, a)
#define CALL_TYPECHECK_5(t, a, ...) \
CALL_TYPECHECK_4(__VA_ARGS__); \
typecheck(t, a)
#define CALL_PARM_0(...) void
#define CALL_PARM_1(t, a, ...) t
#define CALL_PARM_2(t, a, ...) t, CALL_PARM_1(__VA_ARGS__)
#define CALL_PARM_3(t, a, ...) t, CALL_PARM_2(__VA_ARGS__)
#define CALL_PARM_4(t, a, ...) t, CALL_PARM_3(__VA_ARGS__)
#define CALL_PARM_5(t, a, ...) t, CALL_PARM_4(__VA_ARGS__)
#define CALL_PARM_6(t, a, ...) t, CALL_PARM_5(__VA_ARGS__)
/*
* Use call_on_stack() to call a function switching to a specified
* stack. Proper sign and zero extension of function arguments is
* done. Usage:
*
* rc = call_on_stack(nr, stack, rettype, fn, t1, a1, t2, a2, ...)
*
* - nr specifies the number of function arguments of fn.
* - stack specifies the stack to be used.
* - fn is the function to be called.
* - rettype is the return type of fn.
* - t1, a1, ... are pairs, where t1 must match the type of the first
* argument of fn, t2 the second, etc. a1 is the corresponding
* first function argument (not name), etc.
*/
#define call_on_stack(nr, stack, rettype, fn, ...) \
({ \
rettype (*__fn)(CALL_PARM_##nr(__VA_ARGS__)) = fn; \
unsigned long frame = current_frame_address(); \
unsigned long __stack = stack; \
unsigned long prev; \
CALL_LARGS_##nr(__VA_ARGS__); \
CALL_REGS_##nr; \
\
CALL_TYPECHECK_##nr(__VA_ARGS__); \
asm volatile( \
" lgr %[_prev],15\n" \
" lg 15,%[_stack]\n" \
" stg %[_frame],%[_bc](15)\n" \
" brasl 14,%[_fn]\n" \
" lgr 15,%[_prev]\n" \
: [_prev] "=&d" (prev), CALL_FMT_##nr \
: [_stack] "R" (__stack), \
[_bc] "i" (offsetof(struct stack_frame, back_chain)), \
[_frame] "d" (frame), \
[_fn] "X" (__fn) : CALL_CLOBBER_##nr); \
(rettype)r2; \
})
#define CALL_ON_STACK_NORETURN(fn, stack) \ #define CALL_ON_STACK_NORETURN(fn, stack) \
({ \ ({ \
asm volatile( \ asm volatile( \

13
drivers/dma-buf/sync_file.c
View File

@ -211,8 +211,8 @@ static struct sync_file *sync_file_merge(const char *name, struct sync_file *a,
struct sync_file *b) struct sync_file *b)
{ {
struct sync_file *sync_file; struct sync_file *sync_file;
struct dma_fence **fences, **nfences, **a_fences, **b_fences; struct dma_fence **fences = NULL, **nfences, **a_fences, **b_fences;
int i, i_a, i_b, num_fences, a_num_fences, b_num_fences; int i = 0, i_a, i_b, num_fences, a_num_fences, b_num_fences;
sync_file = sync_file_alloc(); sync_file = sync_file_alloc();
if (!sync_file) if (!sync_file)
@ -236,7 +236,7 @@ static struct sync_file *sync_file_merge(const char *name, struct sync_file *a,
* If a sync_file can only be created with sync_file_merge * If a sync_file can only be created with sync_file_merge
* and sync_file_create, this is a reasonable assumption. * and sync_file_create, this is a reasonable assumption.
*/ */
for (i = i_a = i_b = 0; i_a < a_num_fences && i_b < b_num_fences; ) { for (i_a = i_b = 0; i_a < a_num_fences && i_b < b_num_fences; ) {
struct dma_fence *pt_a = a_fences[i_a]; struct dma_fence *pt_a = a_fences[i_a];
struct dma_fence *pt_b = b_fences[i_b]; struct dma_fence *pt_b = b_fences[i_b];
@ -278,15 +278,16 @@ static struct sync_file *sync_file_merge(const char *name, struct sync_file *a,
fences = nfences; fences = nfences;
} }
if (sync_file_set_fence(sync_file, fences, i) < 0) { if (sync_file_set_fence(sync_file, fences, i) < 0)
kfree(fences);
goto err; goto err;
}
strlcpy(sync_file->user_name, name, sizeof(sync_file->user_name)); strlcpy(sync_file->user_name, name, sizeof(sync_file->user_name));
return sync_file; return sync_file;
err: err:
while (i)
dma_fence_put(fences[--i]);
kfree(fences);
fput(sync_file->file); fput(sync_file->file);
return NULL; return NULL;

1
drivers/firmware/tegra/Makefile
View File

@ -3,6 +3,7 @@ tegra-bpmp-y = bpmp.o
tegra-bpmp-$(CONFIG_ARCH_TEGRA_210_SOC) += bpmp-tegra210.o tegra-bpmp-$(CONFIG_ARCH_TEGRA_210_SOC) += bpmp-tegra210.o
tegra-bpmp-$(CONFIG_ARCH_TEGRA_186_SOC) += bpmp-tegra186.o tegra-bpmp-$(CONFIG_ARCH_TEGRA_186_SOC) += bpmp-tegra186.o
tegra-bpmp-$(CONFIG_ARCH_TEGRA_194_SOC) += bpmp-tegra186.o tegra-bpmp-$(CONFIG_ARCH_TEGRA_194_SOC) += bpmp-tegra186.o
tegra-bpmp-$(CONFIG_ARCH_TEGRA_234_SOC) += bpmp-tegra186.o
tegra-bpmp-$(CONFIG_DEBUG_FS) += bpmp-debugfs.o tegra-bpmp-$(CONFIG_DEBUG_FS) += bpmp-debugfs.o
obj-$(CONFIG_TEGRA_BPMP) += tegra-bpmp.o obj-$(CONFIG_TEGRA_BPMP) += tegra-bpmp.o
obj-$(CONFIG_TEGRA_IVC) += ivc.o obj-$(CONFIG_TEGRA_IVC) += ivc.o

3
drivers/firmware/tegra/bpmp-private.h
View File

@ -24,7 +24,8 @@ struct tegra_bpmp_ops {
}; };
#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) || \ #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) || \
IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
extern const struct tegra_bpmp_ops tegra186_bpmp_ops; extern const struct tegra_bpmp_ops tegra186_bpmp_ops;
#endif #endif
#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)

3
drivers/firmware/tegra/bpmp.c
View File

@ -808,7 +808,8 @@ static const struct dev_pm_ops tegra_bpmp_pm_ops = {
}; };
#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) || \ #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) || \
IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
static const struct tegra_bpmp_soc tegra186_soc = { static const struct tegra_bpmp_soc tegra186_soc = {
.channels = { .channels = {
.cpu_tx = { .cpu_tx = {

1
drivers/firmware/turris-mox-rwtm.c
View File

@ -401,6 +401,7 @@ static int turris_mox_rwtm_remove(struct platform_device *pdev)
static const struct of_device_id turris_mox_rwtm_match[] = { static const struct of_device_id turris_mox_rwtm_match[] = {
{ .compatible = "cznic,turris-mox-rwtm", }, { .compatible = "cznic,turris-mox-rwtm", },
{ .compatible = "marvell,armada-3700-rwtm-firmware", },
{ }, { },
}; };

32
drivers/md/dm-writecache.c
View File

@ -154,6 +154,7 @@ struct dm_writecache {
bool overwrote_committed:1; bool overwrote_committed:1;
bool memory_vmapped:1; bool memory_vmapped:1;
bool start_sector_set:1;
bool high_wm_percent_set:1; bool high_wm_percent_set:1;
bool low_wm_percent_set:1; bool low_wm_percent_set:1;
bool max_writeback_jobs_set:1; bool max_writeback_jobs_set:1;
@ -162,6 +163,10 @@ struct dm_writecache {
bool writeback_fua_set:1; bool writeback_fua_set:1;
bool flush_on_suspend:1; bool flush_on_suspend:1;
unsigned high_wm_percent_value;
unsigned low_wm_percent_value;
unsigned autocommit_time_value;
unsigned writeback_all; unsigned writeback_all;
struct workqueue_struct *writeback_wq; struct workqueue_struct *writeback_wq;
struct work_struct writeback_work; struct work_struct writeback_work;
@ -2069,6 +2074,7 @@ static int writecache_ctr(struct dm_target *ti, unsigned argc, char **argv)
if (sscanf(string, "%llu%c", &start_sector, &dummy) != 1) if (sscanf(string, "%llu%c", &start_sector, &dummy) != 1)
goto invalid_optional; goto invalid_optional;
wc->start_sector = start_sector; wc->start_sector = start_sector;
wc->start_sector_set = true;
if (wc->start_sector != start_sector || if (wc->start_sector != start_sector ||
wc->start_sector >= wc->memory_map_size >> SECTOR_SHIFT) wc->start_sector >= wc->memory_map_size >> SECTOR_SHIFT)
goto invalid_optional; goto invalid_optional;
@ -2078,6 +2084,7 @@ static int writecache_ctr(struct dm_target *ti, unsigned argc, char **argv)
goto invalid_optional; goto invalid_optional;
if (high_wm_percent < 0 || high_wm_percent > 100) if (high_wm_percent < 0 || high_wm_percent > 100)
goto invalid_optional; goto invalid_optional;
wc->high_wm_percent_value = high_wm_percent;
wc->high_wm_percent_set = true; wc->high_wm_percent_set = true;
} else if (!strcasecmp(string, "low_watermark") && opt_params >= 1) { } else if (!strcasecmp(string, "low_watermark") && opt_params >= 1) {
string = dm_shift_arg(&as), opt_params--; string = dm_shift_arg(&as), opt_params--;
@ -2085,6 +2092,7 @@ static int writecache_ctr(struct dm_target *ti, unsigned argc, char **argv)
goto invalid_optional; goto invalid_optional;
if (low_wm_percent < 0 || low_wm_percent > 100) if (low_wm_percent < 0 || low_wm_percent > 100)
goto invalid_optional; goto invalid_optional;
wc->low_wm_percent_value = low_wm_percent;
wc->low_wm_percent_set = true; wc->low_wm_percent_set = true;
} else if (!strcasecmp(string, "writeback_jobs") && opt_params >= 1) { } else if (!strcasecmp(string, "writeback_jobs") && opt_params >= 1) {
string = dm_shift_arg(&as), opt_params--; string = dm_shift_arg(&as), opt_params--;
@ -2104,6 +2112,7 @@ static int writecache_ctr(struct dm_target *ti, unsigned argc, char **argv)
if (autocommit_msecs > 3600000) if (autocommit_msecs > 3600000)
goto invalid_optional; goto invalid_optional;
wc->autocommit_jiffies = msecs_to_jiffies(autocommit_msecs); wc->autocommit_jiffies = msecs_to_jiffies(autocommit_msecs);
wc->autocommit_time_value = autocommit_msecs;
wc->autocommit_time_set = true; wc->autocommit_time_set = true;
} else if (!strcasecmp(string, "fua")) { } else if (!strcasecmp(string, "fua")) {
if (WC_MODE_PMEM(wc)) { if (WC_MODE_PMEM(wc)) {
@ -2305,7 +2314,6 @@ static void writecache_status(struct dm_target *ti, status_type_t type,
struct dm_writecache *wc = ti->private; struct dm_writecache *wc = ti->private;
unsigned extra_args; unsigned extra_args;
unsigned sz = 0; unsigned sz = 0;
uint64_t x;
switch (type) { switch (type) {
case STATUSTYPE_INFO: case STATUSTYPE_INFO:
@ -2317,7 +2325,7 @@ static void writecache_status(struct dm_target *ti, status_type_t type,
DMEMIT("%c %s %s %u ", WC_MODE_PMEM(wc) ? 'p' : 's', DMEMIT("%c %s %s %u ", WC_MODE_PMEM(wc) ? 'p' : 's',
wc->dev->name, wc->ssd_dev->name, wc->block_size); wc->dev->name, wc->ssd_dev->name, wc->block_size);
extra_args = 0; extra_args = 0;
if (wc->start_sector) if (wc->start_sector_set)
extra_args += 2; extra_args += 2;
if (wc->high_wm_percent_set) if (wc->high_wm_percent_set)
extra_args += 2; extra_args += 2;
@ -2333,26 +2341,18 @@ static void writecache_status(struct dm_target *ti, status_type_t type,
extra_args++; extra_args++;
DMEMIT("%u", extra_args); DMEMIT("%u", extra_args);
if (wc->start_sector) if (wc->start_sector_set)
DMEMIT(" start_sector %llu", (unsigned long long)wc->start_sector); DMEMIT(" start_sector %llu", (unsigned long long)wc->start_sector);
if (wc->high_wm_percent_set) { if (wc->high_wm_percent_set)
x = (uint64_t)wc->freelist_high_watermark * 100; DMEMIT(" high_watermark %u", wc->high_wm_percent_value);
x += wc->n_blocks / 2; if (wc->low_wm_percent_set)
do_div(x, (size_t)wc->n_blocks); DMEMIT(" low_watermark %u", wc->low_wm_percent_value);
DMEMIT(" high_watermark %u", 100 - (unsigned)x);
}
if (wc->low_wm_percent_set) {
x = (uint64_t)wc->freelist_low_watermark * 100;
x += wc->n_blocks / 2;
do_div(x, (size_t)wc->n_blocks);
DMEMIT(" low_watermark %u", 100 - (unsigned)x);
}
if (wc->max_writeback_jobs_set) if (wc->max_writeback_jobs_set)
DMEMIT(" writeback_jobs %u", wc->max_writeback_jobs); DMEMIT(" writeback_jobs %u", wc->max_writeback_jobs);
if (wc->autocommit_blocks_set) if (wc->autocommit_blocks_set)
DMEMIT(" autocommit_blocks %u", wc->autocommit_blocks); DMEMIT(" autocommit_blocks %u", wc->autocommit_blocks);
if (wc->autocommit_time_set) if (wc->autocommit_time_set)
DMEMIT(" autocommit_time %u", jiffies_to_msecs(wc->autocommit_jiffies)); DMEMIT(" autocommit_time %u", wc->autocommit_time_value);
if (wc->writeback_fua_set) if (wc->writeback_fua_set)
DMEMIT(" %sfua", wc->writeback_fua ? "" : "no"); DMEMIT(" %sfua", wc->writeback_fua ? "" : "no");
break; break;

4
drivers/net/dsa/mv88e6xxx/chip.c
View File

@ -3715,6 +3715,7 @@ static const struct mv88e6xxx_ops mv88e6250_ops = {
.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
.port_set_speed = mv88e6250_port_set_speed, .port_set_speed = mv88e6250_port_set_speed,
.port_tag_remap = mv88e6095_port_tag_remap, .port_tag_remap = mv88e6095_port_tag_remap,
.port_set_policy = mv88e6352_port_set_policy,
.port_set_frame_mode = mv88e6351_port_set_frame_mode, .port_set_frame_mode = mv88e6351_port_set_frame_mode,
.port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_ether_type = mv88e6351_port_set_ether_type,
@ -3916,6 +3917,7 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {
.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
.pot_clear = mv88e6xxx_g2_pot_clear, .pot_clear = mv88e6xxx_g2_pot_clear,
.reset = mv88e6352_g1_reset, .reset = mv88e6352_g1_reset,
.rmu_disable = mv88e6390_g1_rmu_disable,
.vtu_getnext = mv88e6352_g1_vtu_getnext, .vtu_getnext = mv88e6352_g1_vtu_getnext,
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
.serdes_power = mv88e6390_serdes_power, .serdes_power = mv88e6390_serdes_power,
@ -3982,6 +3984,7 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
.port_set_speed = mv88e6185_port_set_speed, .port_set_speed = mv88e6185_port_set_speed,
.port_tag_remap = mv88e6095_port_tag_remap, .port_tag_remap = mv88e6095_port_tag_remap,
.port_set_policy = mv88e6352_port_set_policy,
.port_set_frame_mode = mv88e6351_port_set_frame_mode, .port_set_frame_mode = mv88e6351_port_set_frame_mode,
.port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_egress_floods = mv88e6352_port_set_egress_floods,
.port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_ether_type = mv88e6351_port_set_ether_type,
@ -4004,6 +4007,7 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
.pot_clear = mv88e6xxx_g2_pot_clear, .pot_clear = mv88e6xxx_g2_pot_clear,
.reset = mv88e6352_g1_reset, .reset = mv88e6352_g1_reset,
.rmu_disable = mv88e6390_g1_rmu_disable,
.vtu_getnext = mv88e6352_g1_vtu_getnext, .vtu_getnext = mv88e6352_g1_vtu_getnext,
.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
.avb_ops = &mv88e6352_avb_ops, .avb_ops = &mv88e6352_avb_ops,

6
drivers/net/ethernet/broadcom/genet/bcmgenet.c
View File

@ -2783,15 +2783,21 @@ static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
/* Returns a reusable dma control register value */ /* Returns a reusable dma control register value */
static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
{ {
unsigned int i;
u32 reg; u32 reg;
u32 dma_ctrl; u32 dma_ctrl;
/* disable DMA */ /* disable DMA */
dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
for (i = 0; i < priv->hw_params->tx_queues; i++)
dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
reg = bcmgenet_tdma_readl(priv, DMA_CTRL); reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
reg &= ~dma_ctrl; reg &= ~dma_ctrl;
bcmgenet_tdma_writel(priv, reg, DMA_CTRL); bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
for (i = 0; i < priv->hw_params->rx_queues; i++)
dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
reg = bcmgenet_rdma_readl(priv, DMA_CTRL); reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
reg &= ~dma_ctrl; reg &= ~dma_ctrl;
bcmgenet_rdma_writel(priv, reg, DMA_CTRL); bcmgenet_rdma_writel(priv, reg, DMA_CTRL);

4
drivers/net/ethernet/moxa/moxart_ether.c
View File

@ -545,10 +545,8 @@ static int moxart_mac_probe(struct platform_device *pdev)
SET_NETDEV_DEV(ndev, &pdev->dev); SET_NETDEV_DEV(ndev, &pdev->dev);
ret = register_netdev(ndev); ret = register_netdev(ndev);
if (ret) { if (ret)
free_netdev(ndev);
goto init_fail; goto init_fail;
}
netdev_dbg(ndev, "%s: IRQ=%d address=%pM\n", netdev_dbg(ndev, "%s: IRQ=%d address=%pM\n",
__func__, ndev->irq, ndev->dev_addr); __func__, ndev->irq, ndev->dev_addr);

3
drivers/net/ethernet/qualcomm/emac/emac.c
View File

@ -745,12 +745,13 @@ static int emac_remove(struct platform_device *pdev)
put_device(&adpt->phydev->mdio.dev); put_device(&adpt->phydev->mdio.dev);
mdiobus_unregister(adpt->mii_bus); mdiobus_unregister(adpt->mii_bus);
free_netdev(netdev);
if (adpt->phy.digital) if (adpt->phy.digital)
iounmap(adpt->phy.digital); iounmap(adpt->phy.digital);
iounmap(adpt->phy.base); iounmap(adpt->phy.base);
free_netdev(netdev);
return 0; return 0;
} }

3
drivers/net/ethernet/ti/tlan.c
View File

@ -314,9 +314,8 @@ static void tlan_remove_one(struct pci_dev *pdev)
pci_release_regions(pdev); pci_release_regions(pdev);
#endif #endif
free_netdev(dev);
cancel_work_sync(&priv->tlan_tqueue); cancel_work_sync(&priv->tlan_tqueue);
free_netdev(dev);
} }
static void tlan_start(struct net_device *dev) static void tlan_start(struct net_device *dev)

3
drivers/net/fddi/defza.c
View File

@ -1504,9 +1504,8 @@ err_out_resource:
release_mem_region(start, len); release_mem_region(start, len);
err_out_kfree: err_out_kfree:
free_netdev(dev);
pr_err("%s: initialization failure, aborting!\n", fp->name); pr_err("%s: initialization failure, aborting!\n", fp->name);
free_netdev(dev);
return ret; return ret;
} }

4
drivers/reset/reset-ti-syscon.c
View File

@ -58,8 +58,8 @@ struct ti_syscon_reset_data {
unsigned int nr_controls; unsigned int nr_controls;
}; };
#define to_ti_syscon_reset_data(rcdev) \ #define to_ti_syscon_reset_data(_rcdev) \
container_of(rcdev, struct ti_syscon_reset_data, rcdev) container_of(_rcdev, struct ti_syscon_reset_data, rcdev)
/** /**
* ti_syscon_reset_assert() - assert device reset * ti_syscon_reset_assert() - assert device reset

4
drivers/rtc/rtc-max77686.c
View File

@ -707,8 +707,8 @@ static int max77686_init_rtc_regmap(struct max77686_rtc_info *info)
add_rtc_irq: add_rtc_irq:
ret = regmap_add_irq_chip(info->rtc_regmap, info->rtc_irq, ret = regmap_add_irq_chip(info->rtc_regmap, info->rtc_irq,
IRQF_TRIGGER_FALLING | IRQF_ONESHOT | IRQF_ONESHOT | IRQF_SHARED,
IRQF_SHARED, 0, info->drv_data->rtc_irq_chip, 0, info->drv_data->rtc_irq_chip,
&info->rtc_irq_data); &info->rtc_irq_data);
if (ret < 0) { if (ret < 0) {
dev_err(info->dev, "Failed to add RTC irq chip: %d\n", ret); dev_err(info->dev, "Failed to add RTC irq chip: %d\n", ret);

1
drivers/rtc/rtc-mxc_v2.c
View File

@ -373,6 +373,7 @@ static const struct of_device_id mxc_ids[] = {
{ .compatible = "fsl,imx53-rtc", }, { .compatible = "fsl,imx53-rtc", },
{} {}
}; };
MODULE_DEVICE_TABLE(of, mxc_ids);
static struct platform_driver mxc_rtc_driver = { static struct platform_driver mxc_rtc_driver = {
.driver = { .driver = {

2
drivers/scsi/aic7xxx/aic7xxx_core.c
View File

@ -493,7 +493,7 @@ ahc_inq(struct ahc_softc *ahc, u_int port)
return ((ahc_inb(ahc, port)) return ((ahc_inb(ahc, port))
| (ahc_inb(ahc, port+1) << 8) | (ahc_inb(ahc, port+1) << 8)
| (ahc_inb(ahc, port+2) << 16) | (ahc_inb(ahc, port+2) << 16)
| (ahc_inb(ahc, port+3) << 24) | (((uint64_t)ahc_inb(ahc, port+3)) << 24)
| (((uint64_t)ahc_inb(ahc, port+4)) << 32) | (((uint64_t)ahc_inb(ahc, port+4)) << 32)
| (((uint64_t)ahc_inb(ahc, port+5)) << 40) | (((uint64_t)ahc_inb(ahc, port+5)) << 40)
| (((uint64_t)ahc_inb(ahc, port+6)) << 48) | (((uint64_t)ahc_inb(ahc, port+6)) << 48)

1
drivers/scsi/aic94xx/aic94xx_init.c
View File

@ -52,6 +52,7 @@ static struct scsi_host_template aic94xx_sht = {
.max_sectors = SCSI_DEFAULT_MAX_SECTORS, .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
.eh_device_reset_handler = sas_eh_device_reset_handler, .eh_device_reset_handler = sas_eh_device_reset_handler,
.eh_target_reset_handler = sas_eh_target_reset_handler, .eh_target_reset_handler = sas_eh_target_reset_handler,
.slave_alloc = sas_slave_alloc,
.target_destroy = sas_target_destroy, .target_destroy = sas_target_destroy,
.ioctl = sas_ioctl, .ioctl = sas_ioctl,
.track_queue_depth = 1, .track_queue_depth = 1,

1
drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
View File

@ -1768,6 +1768,7 @@ static struct scsi_host_template sht_v1_hw = {
.max_sectors = SCSI_DEFAULT_MAX_SECTORS, .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
.eh_device_reset_handler = sas_eh_device_reset_handler, .eh_device_reset_handler = sas_eh_device_reset_handler,
.eh_target_reset_handler = sas_eh_target_reset_handler, .eh_target_reset_handler = sas_eh_target_reset_handler,
.slave_alloc = sas_slave_alloc,
.target_destroy = sas_target_destroy, .target_destroy = sas_target_destroy,
.ioctl = sas_ioctl, .ioctl = sas_ioctl,
.shost_attrs = host_attrs_v1_hw, .shost_attrs = host_attrs_v1_hw,

1
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c
View File

@ -3542,6 +3542,7 @@ static struct scsi_host_template sht_v2_hw = {
.max_sectors = SCSI_DEFAULT_MAX_SECTORS, .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
.eh_device_reset_handler = sas_eh_device_reset_handler, .eh_device_reset_handler = sas_eh_device_reset_handler,
.eh_target_reset_handler = sas_eh_target_reset_handler, .eh_target_reset_handler = sas_eh_target_reset_handler,
.slave_alloc = sas_slave_alloc,
.target_destroy = sas_target_destroy, .target_destroy = sas_target_destroy,
.ioctl = sas_ioctl, .ioctl = sas_ioctl,
.shost_attrs = host_attrs_v2_hw, .shost_attrs = host_attrs_v2_hw,

1
drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
View File

@ -3064,6 +3064,7 @@ static struct scsi_host_template sht_v3_hw = {
.max_sectors = SCSI_DEFAULT_MAX_SECTORS, .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
.eh_device_reset_handler = sas_eh_device_reset_handler, .eh_device_reset_handler = sas_eh_device_reset_handler,
.eh_target_reset_handler = sas_eh_target_reset_handler, .eh_target_reset_handler = sas_eh_target_reset_handler,
.slave_alloc = sas_slave_alloc,
.target_destroy = sas_target_destroy, .target_destroy = sas_target_destroy,
.ioctl = sas_ioctl, .ioctl = sas_ioctl,
.shost_attrs = host_attrs_v3_hw, .shost_attrs = host_attrs_v3_hw,

1
drivers/scsi/isci/init.c
View File

@ -166,6 +166,7 @@ static struct scsi_host_template isci_sht = {
.eh_abort_handler = sas_eh_abort_handler, .eh_abort_handler = sas_eh_abort_handler,
.eh_device_reset_handler = sas_eh_device_reset_handler, .eh_device_reset_handler = sas_eh_device_reset_handler,
.eh_target_reset_handler = sas_eh_target_reset_handler, .eh_target_reset_handler = sas_eh_target_reset_handler,
.slave_alloc = sas_slave_alloc,
.target_destroy = sas_target_destroy, .target_destroy = sas_target_destroy,
.ioctl = sas_ioctl, .ioctl = sas_ioctl,
.shost_attrs = isci_host_attrs, .shost_attrs = isci_host_attrs,

13
drivers/scsi/libfc/fc_rport.c
View File

@ -1160,6 +1160,7 @@ static void fc_rport_prli_resp(struct fc_seq *sp, struct fc_frame *fp,
resp_code = (pp->spp.spp_flags & FC_SPP_RESP_MASK); resp_code = (pp->spp.spp_flags & FC_SPP_RESP_MASK);
FC_RPORT_DBG(rdata, "PRLI spp_flags = 0x%x spp_type 0x%x\n", FC_RPORT_DBG(rdata, "PRLI spp_flags = 0x%x spp_type 0x%x\n",
pp->spp.spp_flags, pp->spp.spp_type); pp->spp.spp_flags, pp->spp.spp_type);
rdata->spp_type = pp->spp.spp_type; rdata->spp_type = pp->spp.spp_type;
if (resp_code != FC_SPP_RESP_ACK) { if (resp_code != FC_SPP_RESP_ACK) {
if (resp_code == FC_SPP_RESP_CONF) if (resp_code == FC_SPP_RESP_CONF)
@ -1182,11 +1183,13 @@ static void fc_rport_prli_resp(struct fc_seq *sp, struct fc_frame *fp,
/* /*
* Call prli provider if we should act as a target * Call prli provider if we should act as a target
*/ */
prov = fc_passive_prov[rdata->spp_type]; if (rdata->spp_type < FC_FC4_PROV_SIZE) {
if (prov) { prov = fc_passive_prov[rdata->spp_type];
memset(&temp_spp, 0, sizeof(temp_spp)); if (prov) {
prov->prli(rdata, pp->prli.prli_spp_len, memset(&temp_spp, 0, sizeof(temp_spp));
&pp->spp, &temp_spp); prov->prli(rdata, pp->prli.prli_spp_len,
&pp->spp, &temp_spp);
}
} }
/* /*
* Check if the image pair could be established * Check if the image pair could be established

9
drivers/scsi/libsas/sas_scsi_host.c
View File

@ -911,6 +911,14 @@ void sas_task_abort(struct sas_task *task)
blk_abort_request(sc->request); blk_abort_request(sc->request);
} }
int sas_slave_alloc(struct scsi_device *sdev)
{
if (dev_is_sata(sdev_to_domain_dev(sdev)) && sdev->lun)
return -ENXIO;
return 0;
}
void sas_target_destroy(struct scsi_target *starget) void sas_target_destroy(struct scsi_target *starget)
{ {
struct domain_device *found_dev = starget->hostdata; struct domain_device *found_dev = starget->hostdata;
@ -957,5 +965,6 @@ EXPORT_SYMBOL_GPL(sas_task_abort);
EXPORT_SYMBOL_GPL(sas_phy_reset); EXPORT_SYMBOL_GPL(sas_phy_reset);
EXPORT_SYMBOL_GPL(sas_eh_device_reset_handler); EXPORT_SYMBOL_GPL(sas_eh_device_reset_handler);
EXPORT_SYMBOL_GPL(sas_eh_target_reset_handler); EXPORT_SYMBOL_GPL(sas_eh_target_reset_handler);
EXPORT_SYMBOL_GPL(sas_slave_alloc);
EXPORT_SYMBOL_GPL(sas_target_destroy); EXPORT_SYMBOL_GPL(sas_target_destroy);
EXPORT_SYMBOL_GPL(sas_ioctl); EXPORT_SYMBOL_GPL(sas_ioctl);

1
drivers/scsi/mvsas/mv_init.c
View File

@ -45,6 +45,7 @@ static struct scsi_host_template mvs_sht = {
.max_sectors = SCSI_DEFAULT_MAX_SECTORS, .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
.eh_device_reset_handler = sas_eh_device_reset_handler, .eh_device_reset_handler = sas_eh_device_reset_handler,
.eh_target_reset_handler = sas_eh_target_reset_handler, .eh_target_reset_handler = sas_eh_target_reset_handler,
.slave_alloc = sas_slave_alloc,
.target_destroy = sas_target_destroy, .target_destroy = sas_target_destroy,
.ioctl = sas_ioctl, .ioctl = sas_ioctl,
.shost_attrs = mvst_host_attrs, .shost_attrs = mvst_host_attrs,

1
drivers/scsi/pm8001/pm8001_init.c
View File

@ -86,6 +86,7 @@ static struct scsi_host_template pm8001_sht = {
.max_sectors = SCSI_DEFAULT_MAX_SECTORS, .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
.eh_device_reset_handler = sas_eh_device_reset_handler, .eh_device_reset_handler = sas_eh_device_reset_handler,
.eh_target_reset_handler = sas_eh_target_reset_handler, .eh_target_reset_handler = sas_eh_target_reset_handler,
.slave_alloc = sas_slave_alloc,
.target_destroy = sas_target_destroy, .target_destroy = sas_target_destroy,
.ioctl = sas_ioctl, .ioctl = sas_ioctl,
.shost_attrs = pm8001_host_attrs, .shost_attrs = pm8001_host_attrs,

22
drivers/scsi/qedf/qedf_io.c
View File

@ -1504,9 +1504,19 @@ void qedf_process_error_detect(struct qedf_ctx *qedf, struct fcoe_cqe *cqe,
{ {
int rval; int rval;
if (io_req == NULL) {
QEDF_INFO(NULL, QEDF_LOG_IO, "io_req is NULL.\n");
return;
}
if (io_req->fcport == NULL) {
QEDF_INFO(NULL, QEDF_LOG_IO, "fcport is NULL.\n");
return;
}
if (!cqe) { if (!cqe) {
QEDF_INFO(&qedf->dbg_ctx, QEDF_LOG_IO, QEDF_INFO(&qedf->dbg_ctx, QEDF_LOG_IO,
"cqe is NULL for io_req %p\n", io_req); "cqe is NULL for io_req %p\n", io_req);
return; return;
} }
@ -1522,6 +1532,16 @@ void qedf_process_error_detect(struct qedf_ctx *qedf, struct fcoe_cqe *cqe,
le32_to_cpu(cqe->cqe_info.err_info.rx_buf_off), le32_to_cpu(cqe->cqe_info.err_info.rx_buf_off),
le32_to_cpu(cqe->cqe_info.err_info.rx_id)); le32_to_cpu(cqe->cqe_info.err_info.rx_id));
/* When flush is active, let the cmds be flushed out from the cleanup context */
if (test_bit(QEDF_RPORT_IN_TARGET_RESET, &io_req->fcport->flags) ||
(test_bit(QEDF_RPORT_IN_LUN_RESET, &io_req->fcport->flags) &&
io_req->sc_cmd->device->lun == (u64)io_req->fcport->lun_reset_lun)) {
QEDF_ERR(&qedf->dbg_ctx,
"Dropping EQE for xid=0x%x as fcport is flushing",
io_req->xid);
return;
}
if (qedf->stop_io_on_error) { if (qedf->stop_io_on_error) {
qedf_stop_all_io(qedf); qedf_stop_all_io(qedf);
return; return;

3
drivers/soc/tegra/fuse/fuse-tegra30.c
View File

@ -36,7 +36,8 @@
defined(CONFIG_ARCH_TEGRA_132_SOC) || \ defined(CONFIG_ARCH_TEGRA_132_SOC) || \
defined(CONFIG_ARCH_TEGRA_210_SOC) || \ defined(CONFIG_ARCH_TEGRA_210_SOC) || \
defined(CONFIG_ARCH_TEGRA_186_SOC) || \ defined(CONFIG_ARCH_TEGRA_186_SOC) || \
defined(CONFIG_ARCH_TEGRA_194_SOC) defined(CONFIG_ARCH_TEGRA_194_SOC) || \
defined(CONFIG_ARCH_TEGRA_234_SOC)
static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset) static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
{ {
if (WARN_ON(!fuse->base)) if (WARN_ON(!fuse->base))

2
drivers/thermal/thermal_core.c
View File

@ -1368,7 +1368,7 @@ free_tz:
EXPORT_SYMBOL_GPL(thermal_zone_device_register); EXPORT_SYMBOL_GPL(thermal_zone_device_register);
/** /**
* thermal_device_unregister - removes the registered thermal zone device * thermal_zone_device_unregister - removes the registered thermal zone device
* @tz: the thermal zone device to remove * @tz: the thermal zone device to remove
*/ */
void thermal_zone_device_unregister(struct thermal_zone_device *tz) void thermal_zone_device_unregister(struct thermal_zone_device *tz)

3
fs/cifs/cifs_dfs_ref.c
View File

@ -151,6 +151,9 @@ char *cifs_compose_mount_options(const char *sb_mountdata,
return ERR_PTR(-EINVAL); return ERR_PTR(-EINVAL);
if (ref) { if (ref) {
if (WARN_ON_ONCE(!ref->node_name || ref->path_consumed < 0))
return ERR_PTR(-EINVAL);
if (strlen(fullpath) - ref->path_consumed) { if (strlen(fullpath) - ref->path_consumed) {
prepath = fullpath + ref->path_consumed; prepath = fullpath + ref->path_consumed;
/* skip initial delimiter */ /* skip initial delimiter */

4
fs/f2fs/sysfs.c
View File

@ -499,7 +499,9 @@ F2FS_FEATURE_RO_ATTR(lost_found, FEAT_LOST_FOUND);
F2FS_FEATURE_RO_ATTR(verity, FEAT_VERITY); F2FS_FEATURE_RO_ATTR(verity, FEAT_VERITY);
#endif #endif
F2FS_FEATURE_RO_ATTR(sb_checksum, FEAT_SB_CHECKSUM); F2FS_FEATURE_RO_ATTR(sb_checksum, FEAT_SB_CHECKSUM);
#ifdef CONFIG_UNICODE
F2FS_FEATURE_RO_ATTR(casefold, FEAT_CASEFOLD); F2FS_FEATURE_RO_ATTR(casefold, FEAT_CASEFOLD);
#endif
#define ATTR_LIST(name) (&f2fs_attr_##name.attr) #define ATTR_LIST(name) (&f2fs_attr_##name.attr)
static struct attribute *f2fs_attrs[] = { static struct attribute *f2fs_attrs[] = {
@ -568,7 +570,9 @@ static struct attribute *f2fs_feat_attrs[] = {
ATTR_LIST(verity), ATTR_LIST(verity),
#endif #endif
ATTR_LIST(sb_checksum), ATTR_LIST(sb_checksum),
#ifdef CONFIG_UNICODE
ATTR_LIST(casefold), ATTR_LIST(casefold),
#endif
NULL, NULL,
}; };
ATTRIBUTE_GROUPS(f2fs_feat); ATTRIBUTE_GROUPS(f2fs_feat);

4
include/net/dst_metadata.h
View File

@ -45,7 +45,9 @@ skb_tunnel_info(const struct sk_buff *skb)
return &md_dst->u.tun_info; return &md_dst->u.tun_info;
dst = skb_dst(skb); dst = skb_dst(skb);
if (dst && dst->lwtstate) if (dst && dst->lwtstate &&
(dst->lwtstate->type == LWTUNNEL_ENCAP_IP ||
dst->lwtstate->type == LWTUNNEL_ENCAP_IP6))
return lwt_tun_info(dst->lwtstate); return lwt_tun_info(dst->lwtstate);
return NULL; return NULL;

2
include/net/ip6_route.h
View File

@ -261,7 +261,7 @@ static inline bool ipv6_anycast_destination(const struct dst_entry *dst,
int ip6_fragment(struct net *net, struct sock *sk, struct sk_buff *skb, int ip6_fragment(struct net *net, struct sock *sk, struct sk_buff *skb,
int (*output)(struct net *, struct sock *, struct sk_buff *)); int (*output)(struct net *, struct sock *, struct sk_buff *));
static inline int ip6_skb_dst_mtu(struct sk_buff *skb) static inline unsigned int ip6_skb_dst_mtu(struct sk_buff *skb)
{ {
int mtu; int mtu;

4
kernel/sched/fair.c
View File

@ -4786,7 +4786,7 @@ static const u64 cfs_bandwidth_slack_period = 5 * NSEC_PER_MSEC;
static int runtime_refresh_within(struct cfs_bandwidth *cfs_b, u64 min_expire) static int runtime_refresh_within(struct cfs_bandwidth *cfs_b, u64 min_expire)
{ {
struct hrtimer *refresh_timer = &cfs_b->period_timer; struct hrtimer *refresh_timer = &cfs_b->period_timer;
u64 remaining; s64 remaining;
/* if the call-back is running a quota refresh is already occurring */ /* if the call-back is running a quota refresh is already occurring */
if (hrtimer_callback_running(refresh_timer)) if (hrtimer_callback_running(refresh_timer))
@ -4794,7 +4794,7 @@ static int runtime_refresh_within(struct cfs_bandwidth *cfs_b, u64 min_expire)
/* is a quota refresh about to occur? */ /* is a quota refresh about to occur? */
remaining = ktime_to_ns(hrtimer_expires_remaining(refresh_timer)); remaining = ktime_to_ns(hrtimer_expires_remaining(refresh_timer));
if (remaining < min_expire) if (remaining < (s64)min_expire)
return 1; return 1;
return 0; return 0;

18
mm/slab_common.c
View File

@ -325,14 +325,6 @@ int slab_unmergeable(struct kmem_cache *s)
if (s->refcount < 0) if (s->refcount < 0)
return 1; return 1;
#ifdef CONFIG_MEMCG_KMEM
/*
* Skip the dying kmem_cache.
*/
if (s->memcg_params.dying)
return 1;
#endif
return 0; return 0;
} }
@ -973,6 +965,16 @@ void kmem_cache_destroy(struct kmem_cache *s)
get_online_mems(); get_online_mems();
mutex_lock(&slab_mutex); mutex_lock(&slab_mutex);
/*
* Another thread referenced it again
*/
if (READ_ONCE(s->refcount)) {
spin_lock_irq(&memcg_kmem_wq_lock);
s->memcg_params.dying = false;
spin_unlock_irq(&memcg_kmem_wq_lock);
goto out_unlock;
}
#endif #endif
err = shutdown_memcg_caches(s); err = shutdown_memcg_caches(s);

17
net/bridge/br_if.c
View File

@ -559,7 +559,7 @@ int br_add_if(struct net_bridge *br, struct net_device *dev,
struct net_bridge_port *p; struct net_bridge_port *p;
int err = 0; int err = 0;
unsigned br_hr, dev_hr; unsigned br_hr, dev_hr;
bool changed_addr; bool changed_addr, fdb_synced = false;
/* Don't allow bridging non-ethernet like devices, or DSA-enabled /* Don't allow bridging non-ethernet like devices, or DSA-enabled
* master network devices since the bridge layer rx_handler prevents * master network devices since the bridge layer rx_handler prevents
@ -635,6 +635,19 @@ int br_add_if(struct net_bridge *br, struct net_device *dev,
list_add_rcu(&p->list, &br->port_list); list_add_rcu(&p->list, &br->port_list);
nbp_update_port_count(br); nbp_update_port_count(br);
if (!br_promisc_port(p) && (p->dev->priv_flags & IFF_UNICAST_FLT)) {
/* When updating the port count we also update all ports'
* promiscuous mode.
* A port leaving promiscuous mode normally gets the bridge's
* fdb synced to the unicast filter (if supported), however,
* `br_port_clear_promisc` does not distinguish between
* non-promiscuous ports and *new* ports, so we need to
* sync explicitly here.
*/
fdb_synced = br_fdb_sync_static(br, p) == 0;
if (!fdb_synced)
netdev_err(dev, "failed to sync bridge static fdb addresses to this port\n");
}
netdev_update_features(br->dev); netdev_update_features(br->dev);
@ -684,6 +697,8 @@ int br_add_if(struct net_bridge *br, struct net_device *dev,
return 0; return 0;
err7: err7:
if (fdb_synced)
br_fdb_unsync_static(br, p);
list_del_rcu(&p->list); list_del_rcu(&p->list);
br_fdb_delete_by_port(br, p, 0, 1); br_fdb_delete_by_port(br, p, 0, 1);
nbp_update_port_count(br); nbp_update_port_count(br);

18
net/ipv4/ip_tunnel.c
View File

@ -317,7 +317,7 @@ static int ip_tunnel_bind_dev(struct net_device *dev)
} }
dev->needed_headroom = t_hlen + hlen; dev->needed_headroom = t_hlen + hlen;
mtu -= t_hlen; mtu -= t_hlen + (dev->type == ARPHRD_ETHER ? dev->hard_header_len : 0);
if (mtu < IPV4_MIN_MTU) if (mtu < IPV4_MIN_MTU)
mtu = IPV4_MIN_MTU; mtu = IPV4_MIN_MTU;
@ -348,6 +348,9 @@ static struct ip_tunnel *ip_tunnel_create(struct net *net,
t_hlen = nt->hlen + sizeof(struct iphdr); t_hlen = nt->hlen + sizeof(struct iphdr);
dev->min_mtu = ETH_MIN_MTU; dev->min_mtu = ETH_MIN_MTU;
dev->max_mtu = IP_MAX_MTU - t_hlen; dev->max_mtu = IP_MAX_MTU - t_hlen;
if (dev->type == ARPHRD_ETHER)
dev->max_mtu -= dev->hard_header_len;
ip_tunnel_add(itn, nt); ip_tunnel_add(itn, nt);
return nt; return nt;
@ -495,11 +498,14 @@ static int tnl_update_pmtu(struct net_device *dev, struct sk_buff *skb,
tunnel_hlen = md ? tunnel_hlen : tunnel->hlen; tunnel_hlen = md ? tunnel_hlen : tunnel->hlen;
pkt_size = skb->len - tunnel_hlen; pkt_size = skb->len - tunnel_hlen;
pkt_size -= dev->type == ARPHRD_ETHER ? dev->hard_header_len : 0;
if (df) if (df) {
mtu = dst_mtu(&rt->dst) - (sizeof(struct iphdr) + tunnel_hlen); mtu = dst_mtu(&rt->dst) - (sizeof(struct iphdr) + tunnel_hlen);
else mtu -= dev->type == ARPHRD_ETHER ? dev->hard_header_len : 0;
} else {
mtu = skb_valid_dst(skb) ? dst_mtu(skb_dst(skb)) : dev->mtu; mtu = skb_valid_dst(skb) ? dst_mtu(skb_dst(skb)) : dev->mtu;
}
if (skb_valid_dst(skb)) if (skb_valid_dst(skb))
skb_dst_update_pmtu_no_confirm(skb, mtu); skb_dst_update_pmtu_no_confirm(skb, mtu);
@ -965,6 +971,9 @@ int __ip_tunnel_change_mtu(struct net_device *dev, int new_mtu, bool strict)
int t_hlen = tunnel->hlen + sizeof(struct iphdr); int t_hlen = tunnel->hlen + sizeof(struct iphdr);
int max_mtu = IP_MAX_MTU - t_hlen; int max_mtu = IP_MAX_MTU - t_hlen;
if (dev->type == ARPHRD_ETHER)
max_mtu -= dev->hard_header_len;
if (new_mtu < ETH_MIN_MTU) if (new_mtu < ETH_MIN_MTU)
return -EINVAL; return -EINVAL;
@ -1142,6 +1151,9 @@ int ip_tunnel_newlink(struct net_device *dev, struct nlattr *tb[],
if (tb[IFLA_MTU]) { if (tb[IFLA_MTU]) {
unsigned int max = IP_MAX_MTU - (nt->hlen + sizeof(struct iphdr)); unsigned int max = IP_MAX_MTU - (nt->hlen + sizeof(struct iphdr));
if (dev->type == ARPHRD_ETHER)
max -= dev->hard_header_len;
mtu = clamp(dev->mtu, (unsigned int)ETH_MIN_MTU, max); mtu = clamp(dev->mtu, (unsigned int)ETH_MIN_MTU, max);
} }

4
net/ipv4/tcp_ipv4.c
View File

@ -343,7 +343,7 @@ void tcp_v4_mtu_reduced(struct sock *sk)
if ((1 << sk->sk_state) & (TCPF_LISTEN | TCPF_CLOSE)) if ((1 << sk->sk_state) & (TCPF_LISTEN | TCPF_CLOSE))
return; return;
mtu = tcp_sk(sk)->mtu_info; mtu = READ_ONCE(tcp_sk(sk)->mtu_info);
dst = inet_csk_update_pmtu(sk, mtu); dst = inet_csk_update_pmtu(sk, mtu);
if (!dst) if (!dst)
return; return;
@ -512,7 +512,7 @@ int tcp_v4_err(struct sk_buff *icmp_skb, u32 info)
if (sk->sk_state == TCP_LISTEN) if (sk->sk_state == TCP_LISTEN)
goto out; goto out;
tp->mtu_info = info; WRITE_ONCE(tp->mtu_info, info);
if (!sock_owned_by_user(sk)) { if (!sock_owned_by_user(sk)) {
tcp_v4_mtu_reduced(sk); tcp_v4_mtu_reduced(sk);
} else { } else {

1
net/ipv4/tcp_output.c
View File

@ -1504,6 +1504,7 @@ int tcp_mtu_to_mss(struct sock *sk, int pmtu)
return __tcp_mtu_to_mss(sk, pmtu) - return __tcp_mtu_to_mss(sk, pmtu) -
(tcp_sk(sk)->tcp_header_len - sizeof(struct tcphdr)); (tcp_sk(sk)->tcp_header_len - sizeof(struct tcphdr));
} }
EXPORT_SYMBOL(tcp_mtu_to_mss);
/* Inverse of above */ /* Inverse of above */
int tcp_mss_to_mtu(struct sock *sk, int mss) int tcp_mss_to_mtu(struct sock *sk, int mss)

6
net/ipv4/udp.c
View File

@ -1043,7 +1043,7 @@ int udp_sendmsg(struct sock *sk, struct msghdr *msg, size_t len)
} }
ipcm_init_sk(&ipc, inet); ipcm_init_sk(&ipc, inet);
ipc.gso_size = up->gso_size; ipc.gso_size = READ_ONCE(up->gso_size);
if (msg->msg_controllen) { if (msg->msg_controllen) {
err = udp_cmsg_send(sk, msg, &ipc.gso_size); err = udp_cmsg_send(sk, msg, &ipc.gso_size);
@ -2590,7 +2590,7 @@ int udp_lib_setsockopt(struct sock *sk, int level, int optname,
case UDP_SEGMENT: case UDP_SEGMENT:
if (val < 0 || val > USHRT_MAX) if (val < 0 || val > USHRT_MAX)
return -EINVAL; return -EINVAL;
up->gso_size = val; WRITE_ONCE(up->gso_size, val);
break; break;
case UDP_GRO: case UDP_GRO:
@ -2692,7 +2692,7 @@ int udp_lib_getsockopt(struct sock *sk, int level, int optname,
break; break;
case UDP_SEGMENT: case UDP_SEGMENT:
val = up->gso_size; val = READ_ONCE(up->gso_size);
break; break;
case UDP_GRO: case UDP_GRO:

23
net/ipv6/tcp_ipv6.c
View File

@ -343,11 +343,20 @@ failure:
static void tcp_v6_mtu_reduced(struct sock *sk) static void tcp_v6_mtu_reduced(struct sock *sk)
{ {
struct dst_entry *dst; struct dst_entry *dst;
u32 mtu;
if ((1 << sk->sk_state) & (TCPF_LISTEN | TCPF_CLOSE)) if ((1 << sk->sk_state) & (TCPF_LISTEN | TCPF_CLOSE))
return; return;
dst = inet6_csk_update_pmtu(sk, tcp_sk(sk)->mtu_info); mtu = READ_ONCE(tcp_sk(sk)->mtu_info);
/* Drop requests trying to increase our current mss.
* Check done in __ip6_rt_update_pmtu() is too late.
*/
if (tcp_mtu_to_mss(sk, mtu) >= tcp_sk(sk)->mss_cache)
return;
dst = inet6_csk_update_pmtu(sk, mtu);
if (!dst) if (!dst)
return; return;
@ -428,6 +437,8 @@ static int tcp_v6_err(struct sk_buff *skb, struct inet6_skb_parm *opt,
} }
if (type == ICMPV6_PKT_TOOBIG) { if (type == ICMPV6_PKT_TOOBIG) {
u32 mtu = ntohl(info);
/* We are not interested in TCP_LISTEN and open_requests /* We are not interested in TCP_LISTEN and open_requests
* (SYN-ACKs send out by Linux are always <576bytes so * (SYN-ACKs send out by Linux are always <576bytes so
* they should go through unfragmented). * they should go through unfragmented).
@ -438,7 +449,11 @@ static int tcp_v6_err(struct sk_buff *skb, struct inet6_skb_parm *opt,
if (!ip6_sk_accept_pmtu(sk)) if (!ip6_sk_accept_pmtu(sk))
goto out; goto out;
tp->mtu_info = ntohl(info); if (mtu < IPV6_MIN_MTU)
goto out;
WRITE_ONCE(tp->mtu_info, mtu);
if (!sock_owned_by_user(sk)) if (!sock_owned_by_user(sk))
tcp_v6_mtu_reduced(sk); tcp_v6_mtu_reduced(sk);
else if (!test_and_set_bit(TCP_MTU_REDUCED_DEFERRED, else if (!test_and_set_bit(TCP_MTU_REDUCED_DEFERRED,
@ -513,8 +528,8 @@ static int tcp_v6_send_synack(const struct sock *sk, struct dst_entry *dst,
opt = ireq->ipv6_opt; opt = ireq->ipv6_opt;
if (!opt) if (!opt)
opt = rcu_dereference(np->opt); opt = rcu_dereference(np->opt);
err = ip6_xmit(sk, skb, fl6, sk->sk_mark, opt, np->tclass, err = ip6_xmit(sk, skb, fl6, skb->mark ? : sk->sk_mark, opt,
sk->sk_priority); np->tclass, sk->sk_priority);
rcu_read_unlock(); rcu_read_unlock();
err = net_xmit_eval(err); err = net_xmit_eval(err);
} }

2
net/ipv6/udp.c
View File

@ -1237,7 +1237,7 @@ int udpv6_sendmsg(struct sock *sk, struct msghdr *msg, size_t len)
int (*getfrag)(void *, char *, int, int, int, struct sk_buff *); int (*getfrag)(void *, char *, int, int, int, struct sk_buff *);
ipcm6_init(&ipc6); ipcm6_init(&ipc6);
ipc6.gso_size = up->gso_size; ipc6.gso_size = READ_ONCE(up->gso_size);
ipc6.sockc.tsflags = sk->sk_tsflags; ipc6.sockc.tsflags = sk->sk_tsflags;
ipc6.sockc.mark = sk->sk_mark; ipc6.sockc.mark = sk->sk_mark;

2
net/ipv6/xfrm6_output.c
View File

@ -144,7 +144,7 @@ static int __xfrm6_output(struct net *net, struct sock *sk, struct sk_buff *skb)
{ {
struct dst_entry *dst = skb_dst(skb); struct dst_entry *dst = skb_dst(skb);
struct xfrm_state *x = dst->xfrm; struct xfrm_state *x = dst->xfrm;
int mtu; unsigned int mtu;
bool toobig; bool toobig;
#ifdef CONFIG_NETFILTER #ifdef CONFIG_NETFILTER

3
net/netfilter/nf_conntrack_netlink.c
View File

@ -211,6 +211,7 @@ static int ctnetlink_dump_helpinfo(struct sk_buff *skb,
if (!help) if (!help)
return 0; return 0;
rcu_read_lock();
helper = rcu_dereference(help->helper); helper = rcu_dereference(help->helper);
if (!helper) if (!helper)
goto out; goto out;
@ -226,9 +227,11 @@ static int ctnetlink_dump_helpinfo(struct sk_buff *skb,
nla_nest_end(skb, nest_helper); nla_nest_end(skb, nest_helper);
out: out:
rcu_read_unlock();
return 0; return 0;
nla_put_failure: nla_put_failure:
rcu_read_unlock();
return -1; return -1;
} }

3
net/sched/act_ct.c
View File

@ -474,7 +474,8 @@ static int tcf_ct_act(struct sk_buff *skb, const struct tc_action *a,
/* This will take care of sending queued events /* This will take care of sending queued events
* even if the connection is already confirmed. * even if the connection is already confirmed.
*/ */
nf_conntrack_confirm(skb); if (nf_conntrack_confirm(skb) != NF_ACCEPT)
goto drop;
} }
out_push: out_push:

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