LF-632 clk: s32v234: Fix "enetpll_dfs3" position in sdhc_sels
According to the RM, MC_CGM_0_AC15_SC[SELCTL] needs to be 0b100 in order to select ENET PLL DFS 4 as the source for SDHC_CLK. Omitting such a position in the parents array will prevent clk_get_rate() (called from sdhci-esdhc-imx.c) from determining the frequency of ipg_clk_perclk. Fixes:fba4afe476
("clk: s32v234: Initial enet clk support") Signed-off-by: Stefan-Gabriel Mirea <stefan-gabriel.mirea@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> (cherry picked from commit6f47d7ee76
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@ -31,7 +31,7 @@ PNAME(lin_sels) = {"firc", "fxosc", "dummy",
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"periphpll_phi0_div3", "dummy", "dummy",
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"dummy", "dummy", "sys6",};
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PNAME(sdhc_sels) = {"firc", "fxosc", "dummy",
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PNAME(sdhc_sels) = {"firc", "fxosc", "dummy", "dummy",
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"enetpll_dfs3",};
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PNAME(enet_sels) = {"firc", "fxosc", "dummy",
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