From 7392a4f58d4da1baab0a01f39ca45da6fd64265c Mon Sep 17 00:00:00 2001 From: Stefan-Gabriel Mirea Date: Tue, 14 Jan 2020 18:34:01 +0200 Subject: [PATCH] LF-632 clk: s32v234: Fix "enetpll_dfs3" position in sdhc_sels According to the RM, MC_CGM_0_AC15_SC[SELCTL] needs to be 0b100 in order to select ENET PLL DFS 4 as the source for SDHC_CLK. Omitting such a position in the parents array will prevent clk_get_rate() (called from sdhci-esdhc-imx.c) from determining the frequency of ipg_clk_perclk. Fixes: fba4afe47600 ("clk: s32v234: Initial enet clk support") Signed-off-by: Stefan-Gabriel Mirea Reviewed-by: Leonard Crestez (cherry picked from commit 6f47d7ee76d533622f91533d80d7dc2e89583199) --- drivers/clk/s32/s32v234/clk.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/s32/s32v234/clk.c b/drivers/clk/s32/s32v234/clk.c index cb5abd54fa2c..ad88c6b45c6b 100644 --- a/drivers/clk/s32/s32v234/clk.c +++ b/drivers/clk/s32/s32v234/clk.c @@ -31,7 +31,7 @@ PNAME(lin_sels) = {"firc", "fxosc", "dummy", "periphpll_phi0_div3", "dummy", "dummy", "dummy", "dummy", "sys6",}; -PNAME(sdhc_sels) = {"firc", "fxosc", "dummy", +PNAME(sdhc_sels) = {"firc", "fxosc", "dummy", "dummy", "enetpll_dfs3",}; PNAME(enet_sels) = {"firc", "fxosc", "dummy",