This is the 5.4.119 stable release
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This commit is contained in:
commit
6602fc5788
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
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||||
VERSION = 5
|
||||
PATCHLEVEL = 4
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||||
SUBLEVEL = 118
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||||
SUBLEVEL = 119
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||||
EXTRAVERSION =
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||||
NAME = Kleptomaniac Octopus
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||||
|
||||
|
|
|
@ -139,7 +139,7 @@
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max77693@66 {
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compatible = "maxim,max77693";
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interrupt-parent = <&gpx1>;
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interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
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interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&max77693_irq>;
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reg = <0x66>;
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@ -187,7 +187,7 @@
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max77693-fuel-gauge@36 {
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compatible = "maxim,max17047";
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interrupt-parent = <&gpx2>;
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interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&max77693_fuel_irq>;
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reg = <0x36>;
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@ -588,7 +588,7 @@
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max77686: max77686_pmic@9 {
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compatible = "maxim,max77686";
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interrupt-parent = <&gpx0>;
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interrupts = <7 IRQ_TYPE_NONE>;
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interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-0 = <&max77686_irq>;
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pinctrl-names = "default";
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reg = <0x09>;
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@ -274,7 +274,7 @@
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max77686: pmic@9 {
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compatible = "maxim,max77686";
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interrupt-parent = <&gpx3>;
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interrupts = <2 IRQ_TYPE_NONE>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&max77686_irq>;
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reg = <0x09>;
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@ -133,7 +133,7 @@
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compatible = "maxim,max77686";
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reg = <0x09>;
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interrupt-parent = <&gpx3>;
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interrupts = <2 IRQ_TYPE_NONE>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&max77686_irq>;
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wakeup-source;
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@ -292,7 +292,7 @@
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max77686: max77686@9 {
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compatible = "maxim,max77686";
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interrupt-parent = <&gpx3>;
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interrupts = <2 IRQ_TYPE_NONE>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&max77686_irq>;
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wakeup-source;
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|
|
|
@ -571,7 +571,7 @@
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clocks = <&sys_clk 6>;
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reset-names = "ether";
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resets = <&sys_rst 6>;
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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local-mac-address = [00 00 00 00 00 00];
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socionext,syscon-phy-mode = <&soc_glue 0>;
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|
|
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@ -336,7 +336,7 @@
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<0x0 0x03D00000 0x0 0x300000>;
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reg-names = "west", "east", "north", "south";
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&tlmm 0 0 175>;
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gpio-ranges = <&tlmm 0 0 176>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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|
|
|
@ -990,8 +990,8 @@
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reg = <1>;
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vin4csi41: endpoint@2 {
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reg = <2>;
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vin4csi41: endpoint@3 {
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reg = <3>;
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remote-endpoint = <&csi41vin4>;
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};
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};
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|
@ -1018,8 +1018,8 @@
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reg = <1>;
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vin5csi41: endpoint@2 {
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reg = <2>;
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vin5csi41: endpoint@3 {
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reg = <3>;
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remote-endpoint = <&csi41vin5>;
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};
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};
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|
@ -1046,8 +1046,8 @@
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reg = <1>;
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vin6csi41: endpoint@2 {
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reg = <2>;
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vin6csi41: endpoint@3 {
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reg = <3>;
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remote-endpoint = <&csi41vin6>;
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};
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};
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|
@ -1074,8 +1074,8 @@
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reg = <1>;
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vin7csi41: endpoint@2 {
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reg = <2>;
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vin7csi41: endpoint@3 {
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reg = <3>;
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remote-endpoint = <&csi41vin7>;
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};
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};
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|
|
|
@ -718,7 +718,7 @@
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clocks = <&sys_clk 6>;
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reset-names = "ether";
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resets = <&sys_rst 6>;
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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local-mac-address = [00 00 00 00 00 00];
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socionext,syscon-phy-mode = <&soc_glue 0>;
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|
|
|
@ -509,7 +509,7 @@
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clocks = <&sys_clk 6>;
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reset-names = "ether";
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resets = <&sys_rst 6>;
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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local-mac-address = [00 00 00 00 00 00];
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socionext,syscon-phy-mode = <&soc_glue 0>;
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|
@ -530,7 +530,7 @@
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clocks = <&sys_clk 7>;
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reset-names = "ether";
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resets = <&sys_rst 7>;
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phy-mode = "rgmii";
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phy-mode = "rgmii-id";
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local-mac-address = [00 00 00 00 00 00];
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socionext,syscon-phy-mode = <&soc_glue 1>;
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|
|
@ -66,6 +66,9 @@ struct pcc_regs {
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#define PCC_INT_ENAB 0x08
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#define PCC_TIMER_INT_CLR 0x80
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#define PCC_TIMER_TIC_EN 0x01
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#define PCC_TIMER_COC_EN 0x02
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#define PCC_TIMER_CLR_OVF 0x04
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#define PCC_LEVEL_ABORT 0x07
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|
|
@ -117,8 +117,10 @@ static irqreturn_t mvme147_timer_int (int irq, void *dev_id)
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unsigned long flags;
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local_irq_save(flags);
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m147_pcc->t1_int_cntrl = PCC_TIMER_INT_CLR;
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m147_pcc->t1_cntrl = PCC_TIMER_CLR_OVF;
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m147_pcc->t1_cntrl = PCC_TIMER_CLR_OVF | PCC_TIMER_COC_EN |
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PCC_TIMER_TIC_EN;
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m147_pcc->t1_int_cntrl = PCC_INT_ENAB | PCC_TIMER_INT_CLR |
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PCC_LEVEL_TIMER1;
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clk_total += PCC_TIMER_CYCLES;
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timer_routine(0, NULL);
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local_irq_restore(flags);
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|
@ -136,10 +138,10 @@ void mvme147_sched_init (irq_handler_t timer_routine)
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/* Init the clock with a value */
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/* The clock counter increments until 0xFFFF then reloads */
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m147_pcc->t1_preload = PCC_TIMER_PRELOAD;
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m147_pcc->t1_cntrl = 0x0; /* clear timer */
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m147_pcc->t1_cntrl = 0x3; /* start timer */
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m147_pcc->t1_int_cntrl = PCC_TIMER_INT_CLR; /* clear pending ints */
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m147_pcc->t1_int_cntrl = PCC_INT_ENAB|PCC_LEVEL_TIMER1;
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m147_pcc->t1_cntrl = PCC_TIMER_CLR_OVF | PCC_TIMER_COC_EN |
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PCC_TIMER_TIC_EN;
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m147_pcc->t1_int_cntrl = PCC_INT_ENAB | PCC_TIMER_INT_CLR |
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PCC_LEVEL_TIMER1;
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clocksource_register_hz(&mvme147_clk, PCC_TIMER_CLOCK_FREQ);
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}
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@ -368,6 +368,7 @@ static u32 clk_total;
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#define PCCTOVR1_COC_EN 0x02
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#define PCCTOVR1_OVR_CLR 0x04
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#define PCCTIC1_INT_LEVEL 6
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#define PCCTIC1_INT_CLR 0x08
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#define PCCTIC1_INT_EN 0x10
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|
@ -377,8 +378,8 @@ static irqreturn_t mvme16x_timer_int (int irq, void *dev_id)
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unsigned long flags;
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local_irq_save(flags);
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out_8(PCCTIC1, in_8(PCCTIC1) | PCCTIC1_INT_CLR);
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out_8(PCCTOVR1, PCCTOVR1_OVR_CLR);
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out_8(PCCTOVR1, PCCTOVR1_OVR_CLR | PCCTOVR1_TIC_EN | PCCTOVR1_COC_EN);
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out_8(PCCTIC1, PCCTIC1_INT_EN | PCCTIC1_INT_CLR | PCCTIC1_INT_LEVEL);
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clk_total += PCC_TIMER_CYCLES;
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timer_routine(0, NULL);
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local_irq_restore(flags);
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|
@ -392,14 +393,15 @@ void mvme16x_sched_init (irq_handler_t timer_routine)
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int irq;
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/* Using PCCchip2 or MC2 chip tick timer 1 */
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out_be32(PCCTCNT1, 0);
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out_be32(PCCTCMP1, PCC_TIMER_CYCLES);
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out_8(PCCTOVR1, in_8(PCCTOVR1) | PCCTOVR1_TIC_EN | PCCTOVR1_COC_EN);
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out_8(PCCTIC1, PCCTIC1_INT_EN | 6);
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if (request_irq(MVME16x_IRQ_TIMER, mvme16x_timer_int, IRQF_TIMER, "timer",
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timer_routine))
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panic ("Couldn't register timer int");
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out_be32(PCCTCNT1, 0);
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out_be32(PCCTCMP1, PCC_TIMER_CYCLES);
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out_8(PCCTOVR1, PCCTOVR1_OVR_CLR | PCCTOVR1_TIC_EN | PCCTOVR1_COC_EN);
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out_8(PCCTIC1, PCCTIC1_INT_EN | PCCTIC1_INT_CLR | PCCTIC1_INT_LEVEL);
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clocksource_register_hz(&mvme16x_clk, PCC_TIMER_CLOCK_FREQ);
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if (brdno == 0x0162 || brdno == 0x172)
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|
|
|
@ -59,7 +59,7 @@
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|||
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periph_cntl: syscon@fff8c008 {
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compatible = "syscon";
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reg = <0xfff8c000 0x4>;
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reg = <0xfff8c008 0x4>;
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native-endian;
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};
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|
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|
|
|
@ -59,7 +59,7 @@
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|||
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||||
periph_cntl: syscon@10000008 {
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compatible = "syscon";
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||||
reg = <0x10000000 0xc>;
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||||
reg = <0x10000008 0x4>;
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native-endian;
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};
|
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|
||||
|
|
|
@ -59,7 +59,7 @@
|
|||
|
||||
periph_cntl: syscon@fffe0008 {
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compatible = "syscon";
|
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reg = <0xfffe0000 0x4>;
|
||||
reg = <0xfffe0008 0x4>;
|
||||
native-endian;
|
||||
};
|
||||
|
||||
|
|
|
@ -59,7 +59,7 @@
|
|||
|
||||
periph_cntl: syscon@10000008 {
|
||||
compatible = "syscon";
|
||||
reg = <0x10000000 0xc>;
|
||||
reg = <0x10000008 0x4>;
|
||||
native-endian;
|
||||
};
|
||||
|
||||
|
|
|
@ -59,7 +59,7 @@
|
|||
|
||||
periph_cntl: syscon@100000008 {
|
||||
compatible = "syscon";
|
||||
reg = <0x10000000 0xc>;
|
||||
reg = <0x10000008 0x4>;
|
||||
native-endian;
|
||||
};
|
||||
|
||||
|
|
|
@ -166,8 +166,13 @@ void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
|
|||
res = hose->mem_resource;
|
||||
break;
|
||||
}
|
||||
if (res != NULL)
|
||||
of_pci_range_to_resource(&range, node, res);
|
||||
if (res != NULL) {
|
||||
res->name = node->full_name;
|
||||
res->flags = range.flags;
|
||||
res->start = range.cpu_addr;
|
||||
res->end = range.cpu_addr + range.size - 1;
|
||||
res->parent = res->child = res->sibling = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -30,6 +30,7 @@
|
|||
#define RALINK_GPIOMODE 0x60
|
||||
|
||||
#define PPLL_CFG1 0x9c
|
||||
#define PPLL_LD BIT(23)
|
||||
|
||||
#define PPLL_DRV 0xa0
|
||||
#define PDRV_SW_SET BIT(31)
|
||||
|
@ -239,8 +240,8 @@ static int mt7620_pci_hw_init(struct platform_device *pdev)
|
|||
rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
|
||||
mdelay(100);
|
||||
|
||||
if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
|
||||
dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
|
||||
if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
|
||||
dev_err(&pdev->dev, "pcie PLL not locked, aborting init\n");
|
||||
reset_control_assert(rstpcie0);
|
||||
rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
|
||||
return -1;
|
||||
|
|
|
@ -180,7 +180,6 @@ static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
|
|||
|
||||
int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
u16 cmd;
|
||||
int irq = -1;
|
||||
|
||||
if (dev->bus->number != 0)
|
||||
|
@ -188,8 +187,6 @@ int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
|||
|
||||
switch (PCI_SLOT(dev->devfn)) {
|
||||
case 0x00:
|
||||
rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
|
||||
(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
|
||||
break;
|
||||
case 0x11:
|
||||
irq = RT288X_CPU_IRQ_PCI;
|
||||
|
@ -201,16 +198,6 @@ int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
|||
break;
|
||||
}
|
||||
|
||||
pci_write_config_byte((struct pci_dev *) dev,
|
||||
PCI_CACHE_LINE_SIZE, 0x14);
|
||||
pci_write_config_byte((struct pci_dev *) dev, PCI_LATENCY_TIMER, 0xFF);
|
||||
pci_read_config_word((struct pci_dev *) dev, PCI_COMMAND, &cmd);
|
||||
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
|
||||
PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
|
||||
PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
|
||||
pci_write_config_word((struct pci_dev *) dev, PCI_COMMAND, cmd);
|
||||
pci_write_config_byte((struct pci_dev *) dev, PCI_INTERRUPT_LINE,
|
||||
dev->irq);
|
||||
return irq;
|
||||
}
|
||||
|
||||
|
@ -251,6 +238,30 @@ static int rt288x_pci_probe(struct platform_device *pdev)
|
|||
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev)
|
||||
{
|
||||
static bool slot0_init;
|
||||
|
||||
/*
|
||||
* Nobody seems to initialize slot 0, but this platform requires it, so
|
||||
* do it once when some other slot is being enabled. The PCI subsystem
|
||||
* should configure other slots properly, so no need to do anything
|
||||
* special for those.
|
||||
*/
|
||||
if (!slot0_init && dev->bus->number == 0) {
|
||||
u16 cmd;
|
||||
u32 bar0;
|
||||
|
||||
slot0_init = true;
|
||||
|
||||
pci_bus_write_config_dword(dev->bus, 0, PCI_BASE_ADDRESS_0,
|
||||
0x08000000);
|
||||
pci_bus_read_config_dword(dev->bus, 0, PCI_BASE_ADDRESS_0,
|
||||
&bar0);
|
||||
|
||||
pci_bus_read_config_word(dev->bus, 0, PCI_COMMAND, &cmd);
|
||||
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
|
||||
pci_bus_write_config_word(dev->bus, 0, PCI_COMMAND, cmd);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -214,7 +214,7 @@ config PPC
|
|||
select HAVE_MEMBLOCK_NODE_MAP
|
||||
select HAVE_MOD_ARCH_SPECIFIC
|
||||
select HAVE_NMI if PERF_EVENTS || (PPC64 && PPC_BOOK3S)
|
||||
select HAVE_HARDLOCKUP_DETECTOR_ARCH if (PPC64 && PPC_BOOK3S)
|
||||
select HAVE_HARDLOCKUP_DETECTOR_ARCH if PPC64 && PPC_BOOK3S && SMP
|
||||
select HAVE_OPROFILE
|
||||
select HAVE_OPTPROBES if PPC64
|
||||
select HAVE_PERF_EVENTS
|
||||
|
|
|
@ -352,6 +352,7 @@ config PPC_EARLY_DEBUG_CPM_ADDR
|
|||
config FAIL_IOMMU
|
||||
bool "Fault-injection capability for IOMMU"
|
||||
depends on FAULT_INJECTION
|
||||
depends on PCI || IBMVIO
|
||||
help
|
||||
Provide fault-injection capability for IOMMU. Each device can
|
||||
be selectively enabled via the fail_iommu property.
|
||||
|
|
|
@ -206,8 +206,10 @@ static inline void radix__set_pte_at(struct mm_struct *mm, unsigned long addr,
|
|||
* from ptesync, it should probably go into update_mmu_cache, rather
|
||||
* than set_pte_at (which is used to set ptes unrelated to faults).
|
||||
*
|
||||
* Spurious faults to vmalloc region are not tolerated, so there is
|
||||
* a ptesync in flush_cache_vmap.
|
||||
* Spurious faults from the kernel memory are not tolerated, so there
|
||||
* is a ptesync in flush_cache_vmap, and __map_kernel_page() follows
|
||||
* the pte update sequence from ISA Book III 6.10 Translation Table
|
||||
* Update Synchronization Requirements.
|
||||
*/
|
||||
}
|
||||
|
||||
|
|
|
@ -279,7 +279,7 @@ static void fadump_show_config(void)
|
|||
* that is required for a kernel to boot successfully.
|
||||
*
|
||||
*/
|
||||
static inline u64 fadump_calculate_reserve_size(void)
|
||||
static __init u64 fadump_calculate_reserve_size(void)
|
||||
{
|
||||
u64 base, size, bootmem_min;
|
||||
int ret;
|
||||
|
|
|
@ -266,7 +266,7 @@ static struct feature_property {
|
|||
};
|
||||
|
||||
#if defined(CONFIG_44x) && defined(CONFIG_PPC_FPU)
|
||||
static inline void identical_pvr_fixup(unsigned long node)
|
||||
static __init void identical_pvr_fixup(unsigned long node)
|
||||
{
|
||||
unsigned int pvr;
|
||||
const char *model = of_get_flat_dt_prop(node, "model", NULL);
|
||||
|
|
|
@ -3638,7 +3638,10 @@ int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
|
|||
vcpu->arch.dec_expires = dec + tb;
|
||||
vcpu->cpu = -1;
|
||||
vcpu->arch.thread_cpu = -1;
|
||||
/* Save guest CTRL register, set runlatch to 1 */
|
||||
vcpu->arch.ctrl = mfspr(SPRN_CTRLF);
|
||||
if (!(vcpu->arch.ctrl & 1))
|
||||
mtspr(SPRN_CTRLT, vcpu->arch.ctrl | 1);
|
||||
|
||||
vcpu->arch.iamr = mfspr(SPRN_IAMR);
|
||||
vcpu->arch.pspb = mfspr(SPRN_PSPB);
|
||||
|
|
|
@ -97,7 +97,7 @@ static int early_map_kernel_page(unsigned long ea, unsigned long pa,
|
|||
|
||||
set_the_pte:
|
||||
set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
|
||||
smp_wmb();
|
||||
asm volatile("ptesync": : :"memory");
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -155,7 +155,7 @@ static int __map_kernel_page(unsigned long ea, unsigned long pa,
|
|||
|
||||
set_the_pte:
|
||||
set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
|
||||
smp_wmb();
|
||||
asm volatile("ptesync": : :"memory");
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -363,8 +363,8 @@ ebb_bhrb:
|
|||
* EBB events are pinned & exclusive, so this should never actually
|
||||
* hit, but we leave it as a fallback in case.
|
||||
*/
|
||||
mask |= CNST_EBB_VAL(ebb);
|
||||
value |= CNST_EBB_MASK;
|
||||
mask |= CNST_EBB_MASK;
|
||||
value |= CNST_EBB_VAL(ebb);
|
||||
|
||||
*maskp = mask;
|
||||
*valp = value;
|
||||
|
|
|
@ -181,7 +181,7 @@ sram_code:
|
|||
udelay: /* r11 - tb_ticks_per_usec, r12 - usecs, overwrites r13 */
|
||||
mullw r12, r12, r11
|
||||
mftb r13 /* start */
|
||||
addi r12, r13, r12 /* end */
|
||||
add r12, r13, r12 /* end */
|
||||
1:
|
||||
mftb r13 /* current */
|
||||
cmp cr0, r13, r12
|
||||
|
|
|
@ -66,6 +66,7 @@ EXPORT_SYMBOL_GPL(init_phb_dynamic);
|
|||
int remove_phb_dynamic(struct pci_controller *phb)
|
||||
{
|
||||
struct pci_bus *b = phb->bus;
|
||||
struct pci_host_bridge *host_bridge = to_pci_host_bridge(b->bridge);
|
||||
struct resource *res;
|
||||
int rc, i;
|
||||
|
||||
|
@ -92,7 +93,8 @@ int remove_phb_dynamic(struct pci_controller *phb)
|
|||
/* Remove the PCI bus and unregister the bridge device from sysfs */
|
||||
phb->bus = NULL;
|
||||
pci_remove_bus(b);
|
||||
device_unregister(b->bridge);
|
||||
host_bridge->bus = NULL;
|
||||
device_unregister(&host_bridge->dev);
|
||||
|
||||
/* Now release the IO resource */
|
||||
if (res->flags & IORESOURCE_IO)
|
||||
|
|
|
@ -257,17 +257,20 @@ notrace void xmon_xive_do_dump(int cpu)
|
|||
xmon_printf("\n");
|
||||
}
|
||||
|
||||
static struct irq_data *xive_get_irq_data(u32 hw_irq)
|
||||
{
|
||||
unsigned int irq = irq_find_mapping(xive_irq_domain, hw_irq);
|
||||
|
||||
return irq ? irq_get_irq_data(irq) : NULL;
|
||||
}
|
||||
|
||||
int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d)
|
||||
{
|
||||
struct irq_chip *chip = irq_data_get_irq_chip(d);
|
||||
int rc;
|
||||
u32 target;
|
||||
u8 prio;
|
||||
u32 lirq;
|
||||
|
||||
if (!is_xive_irq(chip))
|
||||
return -EINVAL;
|
||||
|
||||
rc = xive_ops->get_irq_config(hw_irq, &target, &prio, &lirq);
|
||||
if (rc) {
|
||||
xmon_printf("IRQ 0x%08x : no config rc=%d\n", hw_irq, rc);
|
||||
|
@ -277,6 +280,9 @@ int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d)
|
|||
xmon_printf("IRQ 0x%08x : target=0x%x prio=%02x lirq=0x%x ",
|
||||
hw_irq, target, prio, lirq);
|
||||
|
||||
if (!d)
|
||||
d = xive_get_irq_data(hw_irq);
|
||||
|
||||
if (d) {
|
||||
struct xive_irq_data *xd = irq_data_get_irq_handler_data(d);
|
||||
u64 val = xive_esb_read(xd, XIVE_ESB_GET);
|
||||
|
|
|
@ -922,9 +922,9 @@ static int __init setup_hwcaps(void)
|
|||
if (MACHINE_HAS_VX) {
|
||||
elf_hwcap |= HWCAP_S390_VXRS;
|
||||
if (test_facility(134))
|
||||
elf_hwcap |= HWCAP_S390_VXRS_EXT;
|
||||
if (test_facility(135))
|
||||
elf_hwcap |= HWCAP_S390_VXRS_BCD;
|
||||
if (test_facility(135))
|
||||
elf_hwcap |= HWCAP_S390_VXRS_EXT;
|
||||
if (test_facility(148))
|
||||
elf_hwcap |= HWCAP_S390_VXRS_EXT2;
|
||||
if (test_facility(152))
|
||||
|
|
|
@ -16,6 +16,23 @@
|
|||
#include <linux/ptrace.h>
|
||||
#include "kvm-s390.h"
|
||||
|
||||
/**
|
||||
* kvm_s390_real_to_abs - convert guest real address to guest absolute address
|
||||
* @prefix - guest prefix
|
||||
* @gra - guest real address
|
||||
*
|
||||
* Returns the guest absolute address that corresponds to the passed guest real
|
||||
* address @gra of by applying the given prefix.
|
||||
*/
|
||||
static inline unsigned long _kvm_s390_real_to_abs(u32 prefix, unsigned long gra)
|
||||
{
|
||||
if (gra < 2 * PAGE_SIZE)
|
||||
gra += prefix;
|
||||
else if (gra >= prefix && gra < prefix + 2 * PAGE_SIZE)
|
||||
gra -= prefix;
|
||||
return gra;
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_s390_real_to_abs - convert guest real address to guest absolute address
|
||||
* @vcpu - guest virtual cpu
|
||||
|
@ -27,13 +44,30 @@
|
|||
static inline unsigned long kvm_s390_real_to_abs(struct kvm_vcpu *vcpu,
|
||||
unsigned long gra)
|
||||
{
|
||||
unsigned long prefix = kvm_s390_get_prefix(vcpu);
|
||||
return _kvm_s390_real_to_abs(kvm_s390_get_prefix(vcpu), gra);
|
||||
}
|
||||
|
||||
if (gra < 2 * PAGE_SIZE)
|
||||
gra += prefix;
|
||||
else if (gra >= prefix && gra < prefix + 2 * PAGE_SIZE)
|
||||
gra -= prefix;
|
||||
return gra;
|
||||
/**
|
||||
* _kvm_s390_logical_to_effective - convert guest logical to effective address
|
||||
* @psw: psw of the guest
|
||||
* @ga: guest logical address
|
||||
*
|
||||
* Convert a guest logical address to an effective address by applying the
|
||||
* rules of the addressing mode defined by bits 31 and 32 of the given PSW
|
||||
* (extendended/basic addressing mode).
|
||||
*
|
||||
* Depending on the addressing mode, the upper 40 bits (24 bit addressing
|
||||
* mode), 33 bits (31 bit addressing mode) or no bits (64 bit addressing
|
||||
* mode) of @ga will be zeroed and the remaining bits will be returned.
|
||||
*/
|
||||
static inline unsigned long _kvm_s390_logical_to_effective(psw_t *psw,
|
||||
unsigned long ga)
|
||||
{
|
||||
if (psw_bits(*psw).eaba == PSW_BITS_AMODE_64BIT)
|
||||
return ga;
|
||||
if (psw_bits(*psw).eaba == PSW_BITS_AMODE_31BIT)
|
||||
return ga & ((1UL << 31) - 1);
|
||||
return ga & ((1UL << 24) - 1);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -52,13 +86,7 @@ static inline unsigned long kvm_s390_real_to_abs(struct kvm_vcpu *vcpu,
|
|||
static inline unsigned long kvm_s390_logical_to_effective(struct kvm_vcpu *vcpu,
|
||||
unsigned long ga)
|
||||
{
|
||||
psw_t *psw = &vcpu->arch.sie_block->gpsw;
|
||||
|
||||
if (psw_bits(*psw).eaba == PSW_BITS_AMODE_64BIT)
|
||||
return ga;
|
||||
if (psw_bits(*psw).eaba == PSW_BITS_AMODE_31BIT)
|
||||
return ga & ((1UL << 31) - 1);
|
||||
return ga & ((1UL << 24) - 1);
|
||||
return _kvm_s390_logical_to_effective(&vcpu->arch.sie_block->gpsw, ga);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -3980,16 +3980,16 @@ static void store_regs(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
|
|||
current->thread.fpu.fpc = vcpu->arch.host_fpregs.fpc;
|
||||
current->thread.fpu.regs = vcpu->arch.host_fpregs.regs;
|
||||
if (MACHINE_HAS_GS) {
|
||||
preempt_disable();
|
||||
__ctl_set_bit(2, 4);
|
||||
if (vcpu->arch.gs_enabled)
|
||||
save_gs_cb(current->thread.gs_cb);
|
||||
preempt_disable();
|
||||
current->thread.gs_cb = vcpu->arch.host_gscb;
|
||||
restore_gs_cb(vcpu->arch.host_gscb);
|
||||
preempt_enable();
|
||||
if (!vcpu->arch.host_gscb)
|
||||
__ctl_clear_bit(2, 4);
|
||||
vcpu->arch.host_gscb = NULL;
|
||||
preempt_enable();
|
||||
}
|
||||
/* SIE will save etoken directly into SDNX and therefore kvm_run */
|
||||
}
|
||||
|
|
|
@ -550,6 +550,7 @@ config X86_UV
|
|||
depends on X86_EXTENDED_PLATFORM
|
||||
depends on NUMA
|
||||
depends on EFI
|
||||
depends on KEXEC_CORE
|
||||
depends on X86_X2APIC
|
||||
depends on PCI
|
||||
---help---
|
||||
|
|
|
@ -81,12 +81,12 @@ static struct attribute_group amd_iommu_events_group = {
|
|||
};
|
||||
|
||||
struct amd_iommu_event_desc {
|
||||
struct kobj_attribute attr;
|
||||
struct device_attribute attr;
|
||||
const char *event;
|
||||
};
|
||||
|
||||
static ssize_t _iommu_event_show(struct kobject *kobj,
|
||||
struct kobj_attribute *attr, char *buf)
|
||||
static ssize_t _iommu_event_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
struct amd_iommu_event_desc *event =
|
||||
container_of(attr, struct amd_iommu_event_desc, attr);
|
||||
|
|
|
@ -626,16 +626,16 @@ static ssize_t reload_store(struct device *dev,
|
|||
if (val != 1)
|
||||
return size;
|
||||
|
||||
tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev, true);
|
||||
if (tmp_ret != UCODE_NEW)
|
||||
return size;
|
||||
|
||||
get_online_cpus();
|
||||
|
||||
ret = check_online_cpus();
|
||||
if (ret)
|
||||
goto put;
|
||||
|
||||
tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev, true);
|
||||
if (tmp_ret != UCODE_NEW)
|
||||
goto put;
|
||||
|
||||
mutex_lock(µcode_mutex);
|
||||
ret = microcode_reload_late();
|
||||
mutex_unlock(µcode_mutex);
|
||||
|
|
|
@ -157,6 +157,8 @@ NOKPROBE_SYMBOL(skip_prefixes);
|
|||
int can_boost(struct insn *insn, void *addr)
|
||||
{
|
||||
kprobe_opcode_t opcode;
|
||||
insn_byte_t prefix;
|
||||
int i;
|
||||
|
||||
if (search_exception_tables((unsigned long)addr))
|
||||
return 0; /* Page fault may occur on this address. */
|
||||
|
@ -169,9 +171,14 @@ int can_boost(struct insn *insn, void *addr)
|
|||
if (insn->opcode.nbytes != 1)
|
||||
return 0;
|
||||
|
||||
/* Can't boost Address-size override prefix */
|
||||
if (unlikely(inat_is_address_size_prefix(insn->attr)))
|
||||
return 0;
|
||||
for_each_insn_prefix(insn, i, prefix) {
|
||||
insn_attr_t attr;
|
||||
|
||||
attr = inat_get_opcode_attribute(prefix);
|
||||
/* Can't boost Address-size override prefix and CS override prefix */
|
||||
if (prefix == 0x2e || inat_is_address_size_prefix(attr))
|
||||
return 0;
|
||||
}
|
||||
|
||||
opcode = insn->opcode.bytes[0];
|
||||
|
||||
|
@ -196,8 +203,8 @@ int can_boost(struct insn *insn, void *addr)
|
|||
/* clear and set flags are boostable */
|
||||
return (opcode == 0xf5 || (0xf7 < opcode && opcode < 0xfe));
|
||||
default:
|
||||
/* CS override prefix and call are not boostable */
|
||||
return (opcode != 0x2e && opcode != 0x9a);
|
||||
/* call is not boostable */
|
||||
return opcode != 0x9a;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -5308,7 +5308,7 @@ static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu *vcpu,
|
|||
|
||||
/* Decode instruction info and find the field to access */
|
||||
vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
|
||||
field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
|
||||
field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
|
||||
|
||||
/* Out-of-range fields always cause a VM exit from L2 to L1 */
|
||||
if (field >> 15)
|
||||
|
|
|
@ -118,23 +118,15 @@ static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
|
|||
*/
|
||||
#define NUM_RETRIES 500ULL
|
||||
|
||||
struct cppc_attr {
|
||||
struct attribute attr;
|
||||
ssize_t (*show)(struct kobject *kobj,
|
||||
struct attribute *attr, char *buf);
|
||||
ssize_t (*store)(struct kobject *kobj,
|
||||
struct attribute *attr, const char *c, ssize_t count);
|
||||
};
|
||||
|
||||
#define define_one_cppc_ro(_name) \
|
||||
static struct cppc_attr _name = \
|
||||
static struct kobj_attribute _name = \
|
||||
__ATTR(_name, 0444, show_##_name, NULL)
|
||||
|
||||
#define to_cpc_desc(a) container_of(a, struct cpc_desc, kobj)
|
||||
|
||||
#define show_cppc_data(access_fn, struct_name, member_name) \
|
||||
static ssize_t show_##member_name(struct kobject *kobj, \
|
||||
struct attribute *attr, char *buf) \
|
||||
struct kobj_attribute *attr, char *buf) \
|
||||
{ \
|
||||
struct cpc_desc *cpc_ptr = to_cpc_desc(kobj); \
|
||||
struct struct_name st_name = {0}; \
|
||||
|
@ -160,7 +152,7 @@ show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf);
|
|||
show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time);
|
||||
|
||||
static ssize_t show_feedback_ctrs(struct kobject *kobj,
|
||||
struct attribute *attr, char *buf)
|
||||
struct kobj_attribute *attr, char *buf)
|
||||
{
|
||||
struct cpc_desc *cpc_ptr = to_cpc_desc(kobj);
|
||||
struct cppc_perf_fb_ctrs fb_ctrs = {0};
|
||||
|
|
|
@ -582,11 +582,13 @@ int ahci_platform_init_host(struct platform_device *pdev,
|
|||
int i, irq, n_ports, rc;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq <= 0) {
|
||||
if (irq < 0) {
|
||||
if (irq != -EPROBE_DEFER)
|
||||
dev_err(dev, "no irq\n");
|
||||
return irq;
|
||||
}
|
||||
if (!irq)
|
||||
return -EINVAL;
|
||||
|
||||
hpriv->irq = irq;
|
||||
|
||||
|
|
|
@ -817,12 +817,19 @@ static int arasan_cf_probe(struct platform_device *pdev)
|
|||
else
|
||||
quirk = CF_BROKEN_UDMA; /* as it is on spear1340 */
|
||||
|
||||
/* if irq is 0, support only PIO */
|
||||
acdev->irq = platform_get_irq(pdev, 0);
|
||||
if (acdev->irq)
|
||||
/*
|
||||
* If there's an error getting IRQ (or we do get IRQ0),
|
||||
* support only PIO
|
||||
*/
|
||||
ret = platform_get_irq(pdev, 0);
|
||||
if (ret > 0) {
|
||||
acdev->irq = ret;
|
||||
irq_handler = arasan_cf_interrupt;
|
||||
else
|
||||
} else if (ret == -EPROBE_DEFER) {
|
||||
return ret;
|
||||
} else {
|
||||
quirk |= CF_BROKEN_MWDMA | CF_BROKEN_UDMA;
|
||||
}
|
||||
|
||||
acdev->pbase = res->start;
|
||||
acdev->vbase = devm_ioremap_nocache(&pdev->dev, res->start,
|
||||
|
|
|
@ -165,8 +165,12 @@ static int ixp4xx_pata_probe(struct platform_device *pdev)
|
|||
return -ENOMEM;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq)
|
||||
if (irq > 0)
|
||||
irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
|
||||
else if (irq < 0)
|
||||
return irq;
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
/* Setup expansion bus chip selects */
|
||||
*data->cs0_cfg = data->cs0_bits;
|
||||
|
|
|
@ -4097,6 +4097,10 @@ static int mv_platform_probe(struct platform_device *pdev)
|
|||
n_ports = mv_platform_data->n_ports;
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
}
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
if (!irq)
|
||||
return -EINVAL;
|
||||
|
||||
host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
|
||||
hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
|
||||
|
|
|
@ -262,21 +262,20 @@ static void node_init_cache_dev(struct node *node)
|
|||
if (!dev)
|
||||
return;
|
||||
|
||||
device_initialize(dev);
|
||||
dev->parent = &node->dev;
|
||||
dev->release = node_cache_release;
|
||||
if (dev_set_name(dev, "memory_side_cache"))
|
||||
goto free_dev;
|
||||
goto put_device;
|
||||
|
||||
if (device_register(dev))
|
||||
goto free_name;
|
||||
if (device_add(dev))
|
||||
goto put_device;
|
||||
|
||||
pm_runtime_no_callbacks(dev);
|
||||
node->cache_dev = dev;
|
||||
return;
|
||||
free_name:
|
||||
kfree_const(dev->kobj.name);
|
||||
free_dev:
|
||||
kfree(dev);
|
||||
put_device:
|
||||
put_device(dev);
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -313,25 +312,24 @@ void node_add_cache(unsigned int nid, struct node_cache_attrs *cache_attrs)
|
|||
return;
|
||||
|
||||
dev = &info->dev;
|
||||
device_initialize(dev);
|
||||
dev->parent = node->cache_dev;
|
||||
dev->release = node_cacheinfo_release;
|
||||
dev->groups = cache_groups;
|
||||
if (dev_set_name(dev, "index%d", cache_attrs->level))
|
||||
goto free_cache;
|
||||
goto put_device;
|
||||
|
||||
info->cache_attrs = *cache_attrs;
|
||||
if (device_register(dev)) {
|
||||
if (device_add(dev)) {
|
||||
dev_warn(&node->dev, "failed to add cache level:%d\n",
|
||||
cache_attrs->level);
|
||||
goto free_name;
|
||||
goto put_device;
|
||||
}
|
||||
pm_runtime_no_callbacks(dev);
|
||||
list_add_tail(&info->node, &node->cache_attrs);
|
||||
return;
|
||||
free_name:
|
||||
kfree_const(dev->kobj.name);
|
||||
free_cache:
|
||||
kfree(info);
|
||||
put_device:
|
||||
put_device(dev);
|
||||
}
|
||||
|
||||
static void node_remove_caches(struct node *node)
|
||||
|
|
|
@ -661,6 +661,7 @@ void regmap_debugfs_exit(struct regmap *map)
|
|||
regmap_debugfs_free_dump_cache(map);
|
||||
mutex_unlock(&map->cache_lock);
|
||||
kfree(map->debugfs_name);
|
||||
map->debugfs_name = NULL;
|
||||
} else {
|
||||
struct regmap_debugfs_node *node, *tmp;
|
||||
|
||||
|
|
|
@ -73,6 +73,7 @@ int null_zone_init(struct nullb_device *dev)
|
|||
void null_zone_exit(struct nullb_device *dev)
|
||||
{
|
||||
kvfree(dev->zones);
|
||||
dev->zones = NULL;
|
||||
}
|
||||
|
||||
int null_zone_report(struct gendisk *disk, sector_t sector,
|
||||
|
|
|
@ -316,6 +316,7 @@ struct xen_blkif {
|
|||
|
||||
struct work_struct free_work;
|
||||
unsigned int nr_ring_pages;
|
||||
bool multi_ref;
|
||||
/* All rings for this device. */
|
||||
struct xen_blkif_ring *rings;
|
||||
unsigned int nr_rings;
|
||||
|
|
|
@ -949,14 +949,17 @@ static int read_per_ring_refs(struct xen_blkif_ring *ring, const char *dir)
|
|||
for (i = 0; i < nr_grefs; i++) {
|
||||
char ring_ref_name[RINGREF_NAME_LEN];
|
||||
|
||||
snprintf(ring_ref_name, RINGREF_NAME_LEN, "ring-ref%u", i);
|
||||
if (blkif->multi_ref)
|
||||
snprintf(ring_ref_name, RINGREF_NAME_LEN, "ring-ref%u", i);
|
||||
else {
|
||||
WARN_ON(i != 0);
|
||||
snprintf(ring_ref_name, RINGREF_NAME_LEN, "ring-ref");
|
||||
}
|
||||
|
||||
err = xenbus_scanf(XBT_NIL, dir, ring_ref_name,
|
||||
"%u", &ring_ref[i]);
|
||||
|
||||
if (err != 1) {
|
||||
if (nr_grefs == 1)
|
||||
break;
|
||||
|
||||
err = -EINVAL;
|
||||
xenbus_dev_fatal(dev, err, "reading %s/%s",
|
||||
dir, ring_ref_name);
|
||||
|
@ -964,18 +967,6 @@ static int read_per_ring_refs(struct xen_blkif_ring *ring, const char *dir)
|
|||
}
|
||||
}
|
||||
|
||||
if (err != 1) {
|
||||
WARN_ON(nr_grefs != 1);
|
||||
|
||||
err = xenbus_scanf(XBT_NIL, dir, "ring-ref", "%u",
|
||||
&ring_ref[0]);
|
||||
if (err != 1) {
|
||||
err = -EINVAL;
|
||||
xenbus_dev_fatal(dev, err, "reading %s/ring-ref", dir);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
err = -ENOMEM;
|
||||
for (i = 0; i < nr_grefs * XEN_BLKIF_REQS_PER_PAGE; i++) {
|
||||
req = kzalloc(sizeof(*req), GFP_KERNEL);
|
||||
|
@ -1079,10 +1070,15 @@ static int connect_ring(struct backend_info *be)
|
|||
blkif->nr_rings, blkif->blk_protocol, protocol,
|
||||
pers_grants ? "persistent grants" : "");
|
||||
|
||||
ring_page_order = xenbus_read_unsigned(dev->otherend,
|
||||
"ring-page-order", 0);
|
||||
|
||||
if (ring_page_order > xen_blkif_max_ring_order) {
|
||||
err = xenbus_scanf(XBT_NIL, dev->otherend, "ring-page-order", "%u",
|
||||
&ring_page_order);
|
||||
if (err != 1) {
|
||||
blkif->nr_ring_pages = 1;
|
||||
blkif->multi_ref = false;
|
||||
} else if (ring_page_order <= xen_blkif_max_ring_order) {
|
||||
blkif->nr_ring_pages = 1 << ring_page_order;
|
||||
blkif->multi_ref = true;
|
||||
} else {
|
||||
err = -EINVAL;
|
||||
xenbus_dev_fatal(dev, err,
|
||||
"requested ring page order %d exceed max:%d",
|
||||
|
@ -1091,8 +1087,6 @@ static int connect_ring(struct backend_info *be)
|
|||
return err;
|
||||
}
|
||||
|
||||
blkif->nr_ring_pages = 1 << ring_page_order;
|
||||
|
||||
if (blkif->nr_rings == 1)
|
||||
return read_per_ring_refs(&blkif->rings[0], dev->otherend);
|
||||
else {
|
||||
|
|
|
@ -353,8 +353,10 @@ static int qcom_ebi2_probe(struct platform_device *pdev)
|
|||
|
||||
/* Figure out the chipselect */
|
||||
ret = of_property_read_u32(child, "reg", &csindex);
|
||||
if (ret)
|
||||
if (ret) {
|
||||
of_node_put(child);
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (csindex > 5) {
|
||||
dev_err(dev,
|
||||
|
|
|
@ -158,12 +158,23 @@ static int tpk_ioctl(struct tty_struct *tty,
|
|||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* TTY operations hangup function.
|
||||
*/
|
||||
static void tpk_hangup(struct tty_struct *tty)
|
||||
{
|
||||
struct ttyprintk_port *tpkp = tty->driver_data;
|
||||
|
||||
tty_port_hangup(&tpkp->port);
|
||||
}
|
||||
|
||||
static const struct tty_operations ttyprintk_ops = {
|
||||
.open = tpk_open,
|
||||
.close = tpk_close,
|
||||
.write = tpk_write,
|
||||
.write_room = tpk_write_room,
|
||||
.ioctl = tpk_ioctl,
|
||||
.hangup = tpk_hangup,
|
||||
};
|
||||
|
||||
static const struct tty_port_operations null_ops = { };
|
||||
|
|
|
@ -58,10 +58,10 @@ static void __iomem *scu_g6_base;
|
|||
static const struct aspeed_gate_data aspeed_g6_gates[] = {
|
||||
/* clk rst name parent flags */
|
||||
[ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
|
||||
[ASPEED_CLK_GATE_ECLK] = { 1, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
|
||||
[ASPEED_CLK_GATE_ECLK] = { 1, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
|
||||
[ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
|
||||
/* vclk parent - dclk/d1clk/hclk/mclk */
|
||||
[ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
|
||||
[ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
|
||||
[ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
|
||||
/* From dpll */
|
||||
[ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
|
||||
|
|
|
@ -84,6 +84,7 @@ struct clk_pm_cpu {
|
|||
void __iomem *reg_div;
|
||||
u8 shift_div;
|
||||
struct regmap *nb_pm_base;
|
||||
unsigned long l1_expiration;
|
||||
};
|
||||
|
||||
#define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw)
|
||||
|
@ -438,33 +439,6 @@ static u8 clk_pm_cpu_get_parent(struct clk_hw *hw)
|
|||
return val;
|
||||
}
|
||||
|
||||
static int clk_pm_cpu_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
|
||||
struct regmap *base = pm_cpu->nb_pm_base;
|
||||
int load_level;
|
||||
|
||||
/*
|
||||
* We set the clock parent only if the DVFS is available but
|
||||
* not enabled.
|
||||
*/
|
||||
if (IS_ERR(base) || armada_3700_pm_dvfs_is_enabled(base))
|
||||
return -EINVAL;
|
||||
|
||||
/* Set the parent clock for all the load level */
|
||||
for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
|
||||
unsigned int reg, mask, val,
|
||||
offset = ARMADA_37XX_NB_TBG_SEL_OFF;
|
||||
|
||||
armada_3700_pm_dvfs_update_regs(load_level, ®, &offset);
|
||||
|
||||
val = index << offset;
|
||||
mask = ARMADA_37XX_NB_TBG_SEL_MASK << offset;
|
||||
regmap_update_bits(base, reg, mask, val);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long clk_pm_cpu_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
|
@ -512,8 +486,10 @@ static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
}
|
||||
|
||||
/*
|
||||
* Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz
|
||||
* respectively) to L0 frequency (1.2 Ghz) requires a significant
|
||||
* Workaround when base CPU frequnecy is 1000 or 1200 MHz
|
||||
*
|
||||
* Switching the CPU from the L2 or L3 frequencies (250/300 or 200 MHz
|
||||
* respectively) to L0 frequency (1/1.2 GHz) requires a significant
|
||||
* amount of time to let VDD stabilize to the appropriate
|
||||
* voltage. This amount of time is large enough that it cannot be
|
||||
* covered by the hardware countdown register. Due to this, the CPU
|
||||
|
@ -523,26 +499,56 @@ static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
* To work around this problem, we prevent switching directly from the
|
||||
* L2/L3 frequencies to the L0 frequency, and instead switch to the L1
|
||||
* frequency in-between. The sequence therefore becomes:
|
||||
* 1. First switch from L2/L3(200/300MHz) to L1(600MHZ)
|
||||
* 1. First switch from L2/L3 (200/250/300 MHz) to L1 (500/600 MHz)
|
||||
* 2. Sleep 20ms for stabling VDD voltage
|
||||
* 3. Then switch from L1(600MHZ) to L0(1200Mhz).
|
||||
* 3. Then switch from L1 (500/600 MHz) to L0 (1000/1200 MHz).
|
||||
*/
|
||||
static void clk_pm_cpu_set_rate_wa(unsigned long rate, struct regmap *base)
|
||||
static void clk_pm_cpu_set_rate_wa(struct clk_pm_cpu *pm_cpu,
|
||||
unsigned int new_level, unsigned long rate,
|
||||
struct regmap *base)
|
||||
{
|
||||
unsigned int cur_level;
|
||||
|
||||
if (rate != 1200 * 1000 * 1000)
|
||||
return;
|
||||
|
||||
regmap_read(base, ARMADA_37XX_NB_CPU_LOAD, &cur_level);
|
||||
cur_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
|
||||
if (cur_level <= ARMADA_37XX_DVFS_LOAD_1)
|
||||
|
||||
if (cur_level == new_level)
|
||||
return;
|
||||
|
||||
/*
|
||||
* System wants to go to L1 on its own. If we are going from L2/L3,
|
||||
* remember when 20ms will expire. If from L0, set the value so that
|
||||
* next switch to L0 won't have to wait.
|
||||
*/
|
||||
if (new_level == ARMADA_37XX_DVFS_LOAD_1) {
|
||||
if (cur_level == ARMADA_37XX_DVFS_LOAD_0)
|
||||
pm_cpu->l1_expiration = jiffies;
|
||||
else
|
||||
pm_cpu->l1_expiration = jiffies + msecs_to_jiffies(20);
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* If we are setting to L2/L3, just invalidate L1 expiration time,
|
||||
* sleeping is not needed.
|
||||
*/
|
||||
if (rate < 1000*1000*1000)
|
||||
goto invalidate_l1_exp;
|
||||
|
||||
/*
|
||||
* We are going to L0 with rate >= 1GHz. Check whether we have been at
|
||||
* L1 for long enough time. If not, go to L1 for 20ms.
|
||||
*/
|
||||
if (pm_cpu->l1_expiration && jiffies >= pm_cpu->l1_expiration)
|
||||
goto invalidate_l1_exp;
|
||||
|
||||
regmap_update_bits(base, ARMADA_37XX_NB_CPU_LOAD,
|
||||
ARMADA_37XX_NB_CPU_LOAD_MASK,
|
||||
ARMADA_37XX_DVFS_LOAD_1);
|
||||
msleep(20);
|
||||
|
||||
invalidate_l1_exp:
|
||||
pm_cpu->l1_expiration = 0;
|
||||
}
|
||||
|
||||
static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
|
@ -576,7 +582,9 @@ static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
reg = ARMADA_37XX_NB_CPU_LOAD;
|
||||
mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
|
||||
|
||||
clk_pm_cpu_set_rate_wa(rate, base);
|
||||
/* Apply workaround when base CPU frequency is 1000 or 1200 MHz */
|
||||
if (parent_rate >= 1000*1000*1000)
|
||||
clk_pm_cpu_set_rate_wa(pm_cpu, load_level, rate, base);
|
||||
|
||||
regmap_update_bits(base, reg, mask, load_level);
|
||||
|
||||
|
@ -590,7 +598,6 @@ static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
|
||||
static const struct clk_ops clk_pm_cpu_ops = {
|
||||
.get_parent = clk_pm_cpu_get_parent,
|
||||
.set_parent = clk_pm_cpu_set_parent,
|
||||
.round_rate = clk_pm_cpu_round_rate,
|
||||
.set_rate = clk_pm_cpu_set_rate,
|
||||
.recalc_rate = clk_pm_cpu_recalc_rate,
|
||||
|
|
|
@ -93,6 +93,7 @@ static const struct of_device_id qcom_a53pll_match_table[] = {
|
|||
{ .compatible = "qcom,msm8916-a53pll" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qcom_a53pll_match_table);
|
||||
|
||||
static struct platform_driver qcom_a53pll_driver = {
|
||||
.probe = qcom_a53pll_probe,
|
||||
|
|
|
@ -31,10 +31,10 @@ static int uniphier_clk_mux_set_parent(struct clk_hw *hw, u8 index)
|
|||
static u8 uniphier_clk_mux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct uniphier_clk_mux *mux = to_uniphier_clk_mux(hw);
|
||||
int num_parents = clk_hw_get_num_parents(hw);
|
||||
unsigned int num_parents = clk_hw_get_num_parents(hw);
|
||||
int ret;
|
||||
unsigned int val;
|
||||
u8 i;
|
||||
unsigned int i;
|
||||
|
||||
ret = regmap_read(mux->regmap, mux->reg, &val);
|
||||
if (ret)
|
||||
|
|
|
@ -103,9 +103,7 @@ static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
|
|||
/* Enable the fractional mode if needed */
|
||||
rate_div = (rate * FRAC_DIV) / *prate;
|
||||
f = rate_div % FRAC_DIV;
|
||||
zynqmp_pll_set_mode(hw, !!f);
|
||||
|
||||
if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
|
||||
if (f) {
|
||||
if (rate > PS_PLL_VCO_MAX) {
|
||||
fbdiv = rate / PS_PLL_VCO_MAX;
|
||||
rate = rate / (fbdiv + 1);
|
||||
|
@ -179,10 +177,12 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
int ret;
|
||||
const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
|
||||
|
||||
if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
|
||||
rate_div = (rate * FRAC_DIV) / parent_rate;
|
||||
rate_div = (rate * FRAC_DIV) / parent_rate;
|
||||
f = rate_div % FRAC_DIV;
|
||||
zynqmp_pll_set_mode(hw, !!f);
|
||||
|
||||
if (f) {
|
||||
m = rate_div / FRAC_DIV;
|
||||
f = rate_div % FRAC_DIV;
|
||||
m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX));
|
||||
rate = parent_rate * m;
|
||||
frac = (parent_rate * f) / FRAC_DIV;
|
||||
|
|
|
@ -25,6 +25,10 @@
|
|||
|
||||
#include "cpufreq-dt.h"
|
||||
|
||||
/* Clk register set */
|
||||
#define ARMADA_37XX_CLK_TBG_SEL 0
|
||||
#define ARMADA_37XX_CLK_TBG_SEL_CPU_OFF 22
|
||||
|
||||
/* Power management in North Bridge register set */
|
||||
#define ARMADA_37XX_NB_L0L1 0x18
|
||||
#define ARMADA_37XX_NB_L2L3 0x1C
|
||||
|
@ -69,6 +73,8 @@
|
|||
#define LOAD_LEVEL_NR 4
|
||||
|
||||
#define MIN_VOLT_MV 1000
|
||||
#define MIN_VOLT_MV_FOR_L1_1000MHZ 1108
|
||||
#define MIN_VOLT_MV_FOR_L1_1200MHZ 1155
|
||||
|
||||
/* AVS value for the corresponding voltage (in mV) */
|
||||
static int avs_map[] = {
|
||||
|
@ -120,10 +126,15 @@ static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq)
|
|||
* will be configured then the DVFS will be enabled.
|
||||
*/
|
||||
static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
|
||||
struct clk *clk, u8 *divider)
|
||||
struct regmap *clk_base, u8 *divider)
|
||||
{
|
||||
u32 cpu_tbg_sel;
|
||||
int load_lvl;
|
||||
struct clk *parent;
|
||||
|
||||
/* Determine to which TBG clock is CPU connected */
|
||||
regmap_read(clk_base, ARMADA_37XX_CLK_TBG_SEL, &cpu_tbg_sel);
|
||||
cpu_tbg_sel >>= ARMADA_37XX_CLK_TBG_SEL_CPU_OFF;
|
||||
cpu_tbg_sel &= ARMADA_37XX_NB_TBG_SEL_MASK;
|
||||
|
||||
for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
|
||||
unsigned int reg, mask, val, offset = 0;
|
||||
|
@ -142,6 +153,11 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
|
|||
mask = (ARMADA_37XX_NB_CLK_SEL_MASK
|
||||
<< ARMADA_37XX_NB_CLK_SEL_OFF);
|
||||
|
||||
/* Set TBG index, for all levels we use the same TBG */
|
||||
val = cpu_tbg_sel << ARMADA_37XX_NB_TBG_SEL_OFF;
|
||||
mask = (ARMADA_37XX_NB_TBG_SEL_MASK
|
||||
<< ARMADA_37XX_NB_TBG_SEL_OFF);
|
||||
|
||||
/*
|
||||
* Set cpu divider based on the pre-computed array in
|
||||
* order to have balanced step.
|
||||
|
@ -160,14 +176,6 @@ static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
|
|||
|
||||
regmap_update_bits(base, reg, mask, val);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set cpu clock source, for all the level we keep the same
|
||||
* clock source that the one already configured. For this one
|
||||
* we need to use the clock framework
|
||||
*/
|
||||
parent = clk_get_parent(clk);
|
||||
clk_set_parent(clk, parent);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -202,6 +210,8 @@ static u32 armada_37xx_avs_val_match(int target_vm)
|
|||
* - L2 & L3 voltage should be about 150mv smaller than L0 voltage.
|
||||
* This function calculates L1 & L2 & L3 AVS values dynamically based
|
||||
* on L0 voltage and fill all AVS values to the AVS value table.
|
||||
* When base CPU frequency is 1000 or 1200 MHz then there is additional
|
||||
* minimal avs value for load L1.
|
||||
*/
|
||||
static void __init armada37xx_cpufreq_avs_configure(struct regmap *base,
|
||||
struct armada_37xx_dvfs *dvfs)
|
||||
|
@ -233,6 +243,19 @@ static void __init armada37xx_cpufreq_avs_configure(struct regmap *base,
|
|||
for (load_level = 1; load_level < LOAD_LEVEL_NR; load_level++)
|
||||
dvfs->avs[load_level] = avs_min;
|
||||
|
||||
/*
|
||||
* Set the avs values for load L0 and L1 when base CPU frequency
|
||||
* is 1000/1200 MHz to its typical initial values according to
|
||||
* the Armada 3700 Hardware Specifications.
|
||||
*/
|
||||
if (dvfs->cpu_freq_max >= 1000*1000*1000) {
|
||||
if (dvfs->cpu_freq_max >= 1200*1000*1000)
|
||||
avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1200MHZ);
|
||||
else
|
||||
avs_min = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1000MHZ);
|
||||
dvfs->avs[0] = dvfs->avs[1] = avs_min;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -252,6 +275,26 @@ static void __init armada37xx_cpufreq_avs_configure(struct regmap *base,
|
|||
target_vm = avs_map[l0_vdd_min] - 150;
|
||||
target_vm = target_vm > MIN_VOLT_MV ? target_vm : MIN_VOLT_MV;
|
||||
dvfs->avs[2] = dvfs->avs[3] = armada_37xx_avs_val_match(target_vm);
|
||||
|
||||
/*
|
||||
* Fix the avs value for load L1 when base CPU frequency is 1000/1200 MHz,
|
||||
* otherwise the CPU gets stuck when switching from load L1 to load L0.
|
||||
* Also ensure that avs value for load L1 is not higher than for L0.
|
||||
*/
|
||||
if (dvfs->cpu_freq_max >= 1000*1000*1000) {
|
||||
u32 avs_min_l1;
|
||||
|
||||
if (dvfs->cpu_freq_max >= 1200*1000*1000)
|
||||
avs_min_l1 = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1200MHZ);
|
||||
else
|
||||
avs_min_l1 = armada_37xx_avs_val_match(MIN_VOLT_MV_FOR_L1_1000MHZ);
|
||||
|
||||
if (avs_min_l1 > dvfs->avs[0])
|
||||
avs_min_l1 = dvfs->avs[0];
|
||||
|
||||
if (dvfs->avs[1] < avs_min_l1)
|
||||
dvfs->avs[1] = avs_min_l1;
|
||||
}
|
||||
}
|
||||
|
||||
static void __init armada37xx_cpufreq_avs_setup(struct regmap *base,
|
||||
|
@ -358,11 +401,16 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
|||
struct platform_device *pdev;
|
||||
unsigned long freq;
|
||||
unsigned int cur_frequency, base_frequency;
|
||||
struct regmap *nb_pm_base, *avs_base;
|
||||
struct regmap *nb_clk_base, *nb_pm_base, *avs_base;
|
||||
struct device *cpu_dev;
|
||||
int load_lvl, ret;
|
||||
struct clk *clk, *parent;
|
||||
|
||||
nb_clk_base =
|
||||
syscon_regmap_lookup_by_compatible("marvell,armada-3700-periph-clock-nb");
|
||||
if (IS_ERR(nb_clk_base))
|
||||
return -ENODEV;
|
||||
|
||||
nb_pm_base =
|
||||
syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
|
||||
|
||||
|
@ -421,7 +469,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
dvfs = armada_37xx_cpu_freq_info_get(cur_frequency);
|
||||
dvfs = armada_37xx_cpu_freq_info_get(base_frequency);
|
||||
if (!dvfs) {
|
||||
clk_put(clk);
|
||||
return -EINVAL;
|
||||
|
@ -439,7 +487,7 @@ static int __init armada37xx_cpufreq_driver_init(void)
|
|||
armada37xx_cpufreq_avs_configure(avs_base, dvfs);
|
||||
armada37xx_cpufreq_avs_setup(avs_base, dvfs);
|
||||
|
||||
armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
|
||||
armada37xx_cpufreq_dvfs_setup(nb_pm_base, nb_clk_base, dvfs->divider);
|
||||
clk_put(clk);
|
||||
|
||||
for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
|
||||
|
@ -473,7 +521,7 @@ disable_dvfs:
|
|||
remove_opp:
|
||||
/* clean-up the already added opp before leaving */
|
||||
while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
|
||||
freq = cur_frequency / dvfs->divider[load_lvl];
|
||||
freq = base_frequency / dvfs->divider[load_lvl];
|
||||
dev_pm_opp_remove(cpu_dev, freq);
|
||||
}
|
||||
|
||||
|
|
|
@ -233,12 +233,12 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
if (ret)
|
||||
goto out_err_free_reg;
|
||||
|
||||
set_bit(ADF_STATUS_PF_RUNNING, &accel_dev->status);
|
||||
|
||||
ret = adf_dev_init(accel_dev);
|
||||
if (ret)
|
||||
goto out_err_dev_shutdown;
|
||||
|
||||
set_bit(ADF_STATUS_PF_RUNNING, &accel_dev->status);
|
||||
|
||||
ret = adf_dev_start(accel_dev);
|
||||
if (ret)
|
||||
goto out_err_dev_stop;
|
||||
|
|
|
@ -233,12 +233,12 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
if (ret)
|
||||
goto out_err_free_reg;
|
||||
|
||||
set_bit(ADF_STATUS_PF_RUNNING, &accel_dev->status);
|
||||
|
||||
ret = adf_dev_init(accel_dev);
|
||||
if (ret)
|
||||
goto out_err_dev_shutdown;
|
||||
|
||||
set_bit(ADF_STATUS_PF_RUNNING, &accel_dev->status);
|
||||
|
||||
ret = adf_dev_start(accel_dev);
|
||||
if (ret)
|
||||
goto out_err_dev_stop;
|
||||
|
|
|
@ -330,19 +330,32 @@ int adf_isr_resource_alloc(struct adf_accel_dev *accel_dev)
|
|||
|
||||
ret = adf_isr_alloc_msix_entry_table(accel_dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (adf_enable_msix(accel_dev))
|
||||
goto err_out;
|
||||
|
||||
if (adf_setup_bh(accel_dev))
|
||||
goto err_out;
|
||||
ret = adf_enable_msix(accel_dev);
|
||||
if (ret)
|
||||
goto err_free_msix_table;
|
||||
|
||||
if (adf_request_irqs(accel_dev))
|
||||
goto err_out;
|
||||
ret = adf_setup_bh(accel_dev);
|
||||
if (ret)
|
||||
goto err_disable_msix;
|
||||
|
||||
ret = adf_request_irqs(accel_dev);
|
||||
if (ret)
|
||||
goto err_cleanup_bh;
|
||||
|
||||
return 0;
|
||||
|
||||
err_cleanup_bh:
|
||||
adf_cleanup_bh(accel_dev);
|
||||
|
||||
err_disable_msix:
|
||||
adf_disable_msix(&accel_dev->accel_pci_dev);
|
||||
|
||||
err_free_msix_table:
|
||||
adf_isr_free_msix_entry_table(accel_dev);
|
||||
|
||||
err_out:
|
||||
adf_isr_resource_free(accel_dev);
|
||||
return -EFAULT;
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(adf_isr_resource_alloc);
|
||||
|
|
|
@ -197,6 +197,7 @@ static int adf_init_ring(struct adf_etr_ring_data *ring)
|
|||
dev_err(&GET_DEV(accel_dev), "Ring address not aligned\n");
|
||||
dma_free_coherent(&GET_DEV(accel_dev), ring_size_bytes,
|
||||
ring->base_addr, ring->dma_addr);
|
||||
ring->base_addr = NULL;
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
|
|
|
@ -304,17 +304,26 @@ int adf_vf_isr_resource_alloc(struct adf_accel_dev *accel_dev)
|
|||
goto err_out;
|
||||
|
||||
if (adf_setup_pf2vf_bh(accel_dev))
|
||||
goto err_out;
|
||||
goto err_disable_msi;
|
||||
|
||||
if (adf_setup_bh(accel_dev))
|
||||
goto err_out;
|
||||
goto err_cleanup_pf2vf_bh;
|
||||
|
||||
if (adf_request_msi_irq(accel_dev))
|
||||
goto err_out;
|
||||
goto err_cleanup_bh;
|
||||
|
||||
return 0;
|
||||
|
||||
err_cleanup_bh:
|
||||
adf_cleanup_bh(accel_dev);
|
||||
|
||||
err_cleanup_pf2vf_bh:
|
||||
adf_cleanup_pf2vf_bh(accel_dev);
|
||||
|
||||
err_disable_msi:
|
||||
adf_disable_msi(accel_dev);
|
||||
|
||||
err_out:
|
||||
adf_vf_isr_resource_free(accel_dev);
|
||||
return -EFAULT;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(adf_vf_isr_resource_alloc);
|
||||
|
|
|
@ -233,12 +233,12 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
if (ret)
|
||||
goto out_err_free_reg;
|
||||
|
||||
set_bit(ADF_STATUS_PF_RUNNING, &accel_dev->status);
|
||||
|
||||
ret = adf_dev_init(accel_dev);
|
||||
if (ret)
|
||||
goto out_err_dev_shutdown;
|
||||
|
||||
set_bit(ADF_STATUS_PF_RUNNING, &accel_dev->status);
|
||||
|
||||
ret = adf_dev_start(accel_dev);
|
||||
if (ret)
|
||||
goto out_err_dev_stop;
|
||||
|
|
|
@ -319,7 +319,7 @@ static int devfreq_set_target(struct devfreq *devfreq, unsigned long new_freq,
|
|||
devfreq->previous_freq = new_freq;
|
||||
|
||||
if (devfreq->suspend_freq)
|
||||
devfreq->resume_freq = cur_freq;
|
||||
devfreq->resume_freq = new_freq;
|
||||
|
||||
return err;
|
||||
}
|
||||
|
|
|
@ -237,6 +237,7 @@ config INTEL_STRATIX10_RSU
|
|||
config QCOM_SCM
|
||||
bool
|
||||
depends on ARM || ARM64
|
||||
depends on HAVE_ARM_SMCCC
|
||||
select RESET_CONTROLLER
|
||||
|
||||
config QCOM_SCM_32
|
||||
|
|
|
@ -20,6 +20,10 @@
|
|||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <linux/kconfig.h>
|
||||
|
||||
#if IS_REACHABLE(CONFIG_AMD_IOMMU_V2)
|
||||
|
||||
#include <linux/printk.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/slab.h>
|
||||
|
@ -358,3 +362,5 @@ int kfd_iommu_add_perf_counters(struct kfd_topology_device *kdev)
|
|||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -23,7 +23,9 @@
|
|||
#ifndef __KFD_IOMMU_H__
|
||||
#define __KFD_IOMMU_H__
|
||||
|
||||
#if defined(CONFIG_AMD_IOMMU_V2_MODULE) || defined(CONFIG_AMD_IOMMU_V2)
|
||||
#include <linux/kconfig.h>
|
||||
|
||||
#if IS_REACHABLE(CONFIG_AMD_IOMMU_V2)
|
||||
|
||||
#define KFD_SUPPORT_IOMMU_V2
|
||||
|
||||
|
@ -46,6 +48,9 @@ static inline int kfd_iommu_check_device(struct kfd_dev *kfd)
|
|||
}
|
||||
static inline int kfd_iommu_device_init(struct kfd_dev *kfd)
|
||||
{
|
||||
#if IS_MODULE(CONFIG_AMD_IOMMU_V2)
|
||||
WARN_ONCE(1, "iommu_v2 module is not usable by built-in KFD");
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -73,6 +78,6 @@ static inline int kfd_iommu_add_perf_counters(struct kfd_topology_device *kdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#endif /* defined(CONFIG_AMD_IOMMU_V2) */
|
||||
#endif /* IS_REACHABLE(CONFIG_AMD_IOMMU_V2) */
|
||||
|
||||
#endif /* __KFD_IOMMU_H__ */
|
||||
|
|
|
@ -2632,6 +2632,23 @@ static int fill_dc_scaling_info(const struct drm_plane_state *state,
|
|||
scaling_info->src_rect.x = state->src_x >> 16;
|
||||
scaling_info->src_rect.y = state->src_y >> 16;
|
||||
|
||||
/*
|
||||
* For reasons we don't (yet) fully understand a non-zero
|
||||
* src_y coordinate into an NV12 buffer can cause a
|
||||
* system hang. To avoid hangs (and maybe be overly cautious)
|
||||
* let's reject both non-zero src_x and src_y.
|
||||
*
|
||||
* We currently know of only one use-case to reproduce a
|
||||
* scenario with non-zero src_x and src_y for NV12, which
|
||||
* is to gesture the YouTube Android app into full screen
|
||||
* on ChromeOS.
|
||||
*/
|
||||
if (state->fb &&
|
||||
state->fb->format->format == DRM_FORMAT_NV12 &&
|
||||
(scaling_info->src_rect.x != 0 ||
|
||||
scaling_info->src_rect.y != 0))
|
||||
return -EINVAL;
|
||||
|
||||
scaling_info->src_rect.width = state->src_w >> 16;
|
||||
if (scaling_info->src_rect.width == 0)
|
||||
return -EINVAL;
|
||||
|
|
|
@ -128,7 +128,7 @@ static bool intel_get_gvt_attrs(struct attribute ***type_attrs,
|
|||
return true;
|
||||
}
|
||||
|
||||
static bool intel_gvt_init_vgpu_type_groups(struct intel_gvt *gvt)
|
||||
static int intel_gvt_init_vgpu_type_groups(struct intel_gvt *gvt)
|
||||
{
|
||||
int i, j;
|
||||
struct intel_vgpu_type *type;
|
||||
|
@ -146,7 +146,7 @@ static bool intel_gvt_init_vgpu_type_groups(struct intel_gvt *gvt)
|
|||
gvt_vgpu_type_groups[i] = group;
|
||||
}
|
||||
|
||||
return true;
|
||||
return 0;
|
||||
|
||||
unwind:
|
||||
for (j = 0; j < i; j++) {
|
||||
|
@ -154,7 +154,7 @@ unwind:
|
|||
kfree(group);
|
||||
}
|
||||
|
||||
return false;
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static void intel_gvt_cleanup_vgpu_type_groups(struct intel_gvt *gvt)
|
||||
|
@ -362,7 +362,7 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv)
|
|||
goto out_clean_thread;
|
||||
|
||||
ret = intel_gvt_init_vgpu_type_groups(gvt);
|
||||
if (ret == false) {
|
||||
if (ret) {
|
||||
gvt_err("failed to init vgpu type groups: %d\n", ret);
|
||||
goto out_clean_types;
|
||||
}
|
||||
|
|
|
@ -494,8 +494,14 @@ static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as,
|
|||
}
|
||||
bo->base.pages = pages;
|
||||
bo->base.pages_use_count = 1;
|
||||
} else
|
||||
} else {
|
||||
pages = bo->base.pages;
|
||||
if (pages[page_offset]) {
|
||||
/* Pages are already mapped, bail out. */
|
||||
mutex_unlock(&bo->base.pages_lock);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
mapping = bo->base.base.filp->f_mapping;
|
||||
mapping_set_unevictable(mapping);
|
||||
|
@ -529,6 +535,7 @@ static int panfrost_mmu_map_fault_addr(struct panfrost_device *pfdev, int as,
|
|||
|
||||
dev_dbg(pfdev->dev, "mapped page fault @ AS%d %llx", as, addr);
|
||||
|
||||
out:
|
||||
panfrost_gem_mapping_put(bomapping);
|
||||
|
||||
return 0;
|
||||
|
@ -600,6 +607,8 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data)
|
|||
access_type = (fault_status >> 8) & 0x3;
|
||||
source_id = (fault_status >> 16);
|
||||
|
||||
mmu_write(pfdev, MMU_INT_CLEAR, mask);
|
||||
|
||||
/* Page fault only */
|
||||
ret = -1;
|
||||
if ((status & mask) == BIT(i) && (exception_type & 0xF8) == 0xC0)
|
||||
|
@ -623,8 +632,6 @@ static irqreturn_t panfrost_mmu_irq_handler_thread(int irq, void *data)
|
|||
access_type, access_type_name(pfdev, fault_status),
|
||||
source_id);
|
||||
|
||||
mmu_write(pfdev, MMU_INT_CLEAR, mask);
|
||||
|
||||
status &= ~mask;
|
||||
}
|
||||
|
||||
|
|
|
@ -512,6 +512,7 @@ static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file
|
|||
*value = rdev->config.si.backend_enable_mask;
|
||||
} else {
|
||||
DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
break;
|
||||
case RADEON_INFO_MAX_SCLK:
|
||||
|
|
|
@ -932,6 +932,7 @@
|
|||
#define USB_DEVICE_ID_ORTEK_IHOME_IMAC_A210S 0x8003
|
||||
|
||||
#define USB_VENDOR_ID_PLANTRONICS 0x047f
|
||||
#define USB_DEVICE_ID_PLANTRONICS_BLACKWIRE_3220_SERIES 0xc056
|
||||
|
||||
#define USB_VENDOR_ID_PANASONIC 0x04da
|
||||
#define USB_DEVICE_ID_PANABOARD_UBT780 0x1044
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <linux/hid.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/jiffies.h>
|
||||
|
||||
#define PLT_HID_1_0_PAGE 0xffa00000
|
||||
#define PLT_HID_2_0_PAGE 0xffa20000
|
||||
|
@ -36,6 +37,16 @@
|
|||
#define PLT_ALLOW_CONSUMER (field->application == HID_CP_CONSUMERCONTROL && \
|
||||
(usage->hid & HID_USAGE_PAGE) == HID_UP_CONSUMER)
|
||||
|
||||
#define PLT_QUIRK_DOUBLE_VOLUME_KEYS BIT(0)
|
||||
|
||||
#define PLT_DOUBLE_KEY_TIMEOUT 5 /* ms */
|
||||
|
||||
struct plt_drv_data {
|
||||
unsigned long device_type;
|
||||
unsigned long last_volume_key_ts;
|
||||
u32 quirks;
|
||||
};
|
||||
|
||||
static int plantronics_input_mapping(struct hid_device *hdev,
|
||||
struct hid_input *hi,
|
||||
struct hid_field *field,
|
||||
|
@ -43,7 +54,8 @@ static int plantronics_input_mapping(struct hid_device *hdev,
|
|||
unsigned long **bit, int *max)
|
||||
{
|
||||
unsigned short mapped_key;
|
||||
unsigned long plt_type = (unsigned long)hid_get_drvdata(hdev);
|
||||
struct plt_drv_data *drv_data = hid_get_drvdata(hdev);
|
||||
unsigned long plt_type = drv_data->device_type;
|
||||
|
||||
/* special case for PTT products */
|
||||
if (field->application == HID_GD_JOYSTICK)
|
||||
|
@ -105,6 +117,30 @@ mapped:
|
|||
return 1;
|
||||
}
|
||||
|
||||
static int plantronics_event(struct hid_device *hdev, struct hid_field *field,
|
||||
struct hid_usage *usage, __s32 value)
|
||||
{
|
||||
struct plt_drv_data *drv_data = hid_get_drvdata(hdev);
|
||||
|
||||
if (drv_data->quirks & PLT_QUIRK_DOUBLE_VOLUME_KEYS) {
|
||||
unsigned long prev_ts, cur_ts;
|
||||
|
||||
/* Usages are filtered in plantronics_usages. */
|
||||
|
||||
if (!value) /* Handle key presses only. */
|
||||
return 0;
|
||||
|
||||
prev_ts = drv_data->last_volume_key_ts;
|
||||
cur_ts = jiffies;
|
||||
if (jiffies_to_msecs(cur_ts - prev_ts) <= PLT_DOUBLE_KEY_TIMEOUT)
|
||||
return 1; /* Ignore the repeated key. */
|
||||
|
||||
drv_data->last_volume_key_ts = cur_ts;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static unsigned long plantronics_device_type(struct hid_device *hdev)
|
||||
{
|
||||
unsigned i, col_page;
|
||||
|
@ -133,15 +169,24 @@ exit:
|
|||
static int plantronics_probe(struct hid_device *hdev,
|
||||
const struct hid_device_id *id)
|
||||
{
|
||||
struct plt_drv_data *drv_data;
|
||||
int ret;
|
||||
|
||||
drv_data = devm_kzalloc(&hdev->dev, sizeof(*drv_data), GFP_KERNEL);
|
||||
if (!drv_data)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = hid_parse(hdev);
|
||||
if (ret) {
|
||||
hid_err(hdev, "parse failed\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
hid_set_drvdata(hdev, (void *)plantronics_device_type(hdev));
|
||||
drv_data->device_type = plantronics_device_type(hdev);
|
||||
drv_data->quirks = id->driver_data;
|
||||
drv_data->last_volume_key_ts = jiffies - msecs_to_jiffies(PLT_DOUBLE_KEY_TIMEOUT);
|
||||
|
||||
hid_set_drvdata(hdev, drv_data);
|
||||
|
||||
ret = hid_hw_start(hdev, HID_CONNECT_DEFAULT |
|
||||
HID_CONNECT_HIDINPUT_FORCE | HID_CONNECT_HIDDEV_FORCE);
|
||||
|
@ -153,15 +198,26 @@ err:
|
|||
}
|
||||
|
||||
static const struct hid_device_id plantronics_devices[] = {
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_PLANTRONICS,
|
||||
USB_DEVICE_ID_PLANTRONICS_BLACKWIRE_3220_SERIES),
|
||||
.driver_data = PLT_QUIRK_DOUBLE_VOLUME_KEYS },
|
||||
{ HID_USB_DEVICE(USB_VENDOR_ID_PLANTRONICS, HID_ANY_ID) },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(hid, plantronics_devices);
|
||||
|
||||
static const struct hid_usage_id plantronics_usages[] = {
|
||||
{ HID_CP_VOLUMEUP, EV_KEY, HID_ANY_ID },
|
||||
{ HID_CP_VOLUMEDOWN, EV_KEY, HID_ANY_ID },
|
||||
{ HID_TERMINATOR, HID_TERMINATOR, HID_TERMINATOR }
|
||||
};
|
||||
|
||||
static struct hid_driver plantronics_driver = {
|
||||
.name = "plantronics",
|
||||
.id_table = plantronics_devices,
|
||||
.usage_table = plantronics_usages,
|
||||
.input_mapping = plantronics_input_mapping,
|
||||
.event = plantronics_event,
|
||||
.probe = plantronics_probe,
|
||||
};
|
||||
module_hid_driver(plantronics_driver);
|
||||
|
|
|
@ -210,8 +210,6 @@ static void hsi_add_client_from_dt(struct hsi_port *port,
|
|||
if (err)
|
||||
goto err;
|
||||
|
||||
dev_set_name(&cl->device, "%s", name);
|
||||
|
||||
err = hsi_of_property_parse_mode(client, "hsi-mode", &mode);
|
||||
if (err) {
|
||||
err = hsi_of_property_parse_mode(client, "hsi-rx-mode",
|
||||
|
@ -293,6 +291,7 @@ static void hsi_add_client_from_dt(struct hsi_port *port,
|
|||
cl->device.release = hsi_client_release;
|
||||
cl->device.of_node = client;
|
||||
|
||||
dev_set_name(&cl->device, "%s", name);
|
||||
if (device_register(&cl->device) < 0) {
|
||||
pr_err("hsi: failed to register client: %s\n", name);
|
||||
put_device(&cl->device);
|
||||
|
|
|
@ -763,6 +763,12 @@ static void init_vp_index(struct vmbus_channel *channel, u16 dev_type)
|
|||
free_cpumask_var(available_mask);
|
||||
}
|
||||
|
||||
#define UNLOAD_DELAY_UNIT_MS 10 /* 10 milliseconds */
|
||||
#define UNLOAD_WAIT_MS (100*1000) /* 100 seconds */
|
||||
#define UNLOAD_WAIT_LOOPS (UNLOAD_WAIT_MS/UNLOAD_DELAY_UNIT_MS)
|
||||
#define UNLOAD_MSG_MS (5*1000) /* Every 5 seconds */
|
||||
#define UNLOAD_MSG_LOOPS (UNLOAD_MSG_MS/UNLOAD_DELAY_UNIT_MS)
|
||||
|
||||
static void vmbus_wait_for_unload(void)
|
||||
{
|
||||
int cpu;
|
||||
|
@ -780,12 +786,17 @@ static void vmbus_wait_for_unload(void)
|
|||
* vmbus_connection.unload_event. If not, the last thing we can do is
|
||||
* read message pages for all CPUs directly.
|
||||
*
|
||||
* Wait no more than 10 seconds so that the panic path can't get
|
||||
* hung forever in case the response message isn't seen.
|
||||
* Wait up to 100 seconds since an Azure host must writeback any dirty
|
||||
* data in its disk cache before the VMbus UNLOAD request will
|
||||
* complete. This flushing has been empirically observed to take up
|
||||
* to 50 seconds in cases with a lot of dirty data, so allow additional
|
||||
* leeway and for inaccuracies in mdelay(). But eventually time out so
|
||||
* that the panic path can't get hung forever in case the response
|
||||
* message isn't seen.
|
||||
*/
|
||||
for (i = 0; i < 1000; i++) {
|
||||
for (i = 1; i <= UNLOAD_WAIT_LOOPS; i++) {
|
||||
if (completion_done(&vmbus_connection.unload_event))
|
||||
break;
|
||||
goto completed;
|
||||
|
||||
for_each_online_cpu(cpu) {
|
||||
struct hv_per_cpu_context *hv_cpu
|
||||
|
@ -808,9 +819,18 @@ static void vmbus_wait_for_unload(void)
|
|||
vmbus_signal_eom(msg, message_type);
|
||||
}
|
||||
|
||||
mdelay(10);
|
||||
}
|
||||
/*
|
||||
* Give a notice periodically so someone watching the
|
||||
* serial output won't think it is completely hung.
|
||||
*/
|
||||
if (!(i % UNLOAD_MSG_LOOPS))
|
||||
pr_notice("Waiting for VMBus UNLOAD to complete\n");
|
||||
|
||||
mdelay(UNLOAD_DELAY_UNIT_MS);
|
||||
}
|
||||
pr_err("Continuing even though VMBus UNLOAD did not complete\n");
|
||||
|
||||
completed:
|
||||
/*
|
||||
* We're crashing and already got the UNLOAD_RESPONSE, cleanup all
|
||||
* maybe-pending messages on all CPUs to be able to receive new
|
||||
|
|
|
@ -901,7 +901,10 @@ static int cdns_i2c_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(id->membase))
|
||||
return PTR_ERR(id->membase);
|
||||
|
||||
id->irq = platform_get_irq(pdev, 0);
|
||||
ret = platform_get_irq(pdev, 0);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
id->irq = ret;
|
||||
|
||||
id->adap.owner = THIS_MODULE;
|
||||
id->adap.dev.of_node = pdev->dev.of_node;
|
||||
|
|
|
@ -397,7 +397,10 @@ static int em_i2c_probe(struct platform_device *pdev)
|
|||
|
||||
em_i2c_reset(&priv->adap);
|
||||
|
||||
priv->irq = platform_get_irq(pdev, 0);
|
||||
ret = platform_get_irq(pdev, 0);
|
||||
if (ret < 0)
|
||||
goto err_clk;
|
||||
priv->irq = ret;
|
||||
ret = devm_request_irq(&pdev->dev, priv->irq, em_i2c_irq_handler, 0,
|
||||
"em_i2c", priv);
|
||||
if (ret)
|
||||
|
|
|
@ -1057,7 +1057,7 @@ static int img_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
|
|||
atomic = true;
|
||||
}
|
||||
|
||||
ret = pm_runtime_get_sync(adap->dev.parent);
|
||||
ret = pm_runtime_resume_and_get(adap->dev.parent);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
@ -1158,7 +1158,7 @@ static int img_i2c_init(struct img_i2c *i2c)
|
|||
u32 rev;
|
||||
int ret;
|
||||
|
||||
ret = pm_runtime_get_sync(i2c->adap.dev.parent);
|
||||
ret = pm_runtime_resume_and_get(i2c->adap.dev.parent);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
|
@ -283,7 +283,7 @@ static int lpi2c_imx_master_enable(struct lpi2c_imx_struct *lpi2c_imx)
|
|||
unsigned int temp;
|
||||
int ret;
|
||||
|
||||
ret = pm_runtime_get_sync(lpi2c_imx->adapter.dev.parent);
|
||||
ret = pm_runtime_resume_and_get(lpi2c_imx->adapter.dev.parent);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
|
@ -751,7 +751,10 @@ static int jz4780_i2c_probe(struct platform_device *pdev)
|
|||
|
||||
jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0x0);
|
||||
|
||||
i2c->irq = platform_get_irq(pdev, 0);
|
||||
ret = platform_get_irq(pdev, 0);
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
i2c->irq = ret;
|
||||
ret = devm_request_irq(&pdev->dev, i2c->irq, jz4780_i2c_irq, 0,
|
||||
dev_name(&pdev->dev), i2c);
|
||||
if (ret)
|
||||
|
|
|
@ -1408,9 +1408,9 @@ omap_i2c_probe(struct platform_device *pdev)
|
|||
pm_runtime_set_autosuspend_delay(omap->dev, OMAP_I2C_PM_TIMEOUT);
|
||||
pm_runtime_use_autosuspend(omap->dev);
|
||||
|
||||
r = pm_runtime_get_sync(omap->dev);
|
||||
r = pm_runtime_resume_and_get(omap->dev);
|
||||
if (r < 0)
|
||||
goto err_free_mem;
|
||||
goto err_disable_pm;
|
||||
|
||||
/*
|
||||
* Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
|
||||
|
@ -1518,8 +1518,8 @@ err_unuse_clocks:
|
|||
omap_i2c_write_reg(omap, OMAP_I2C_CON_REG, 0);
|
||||
pm_runtime_dont_use_autosuspend(omap->dev);
|
||||
pm_runtime_put_sync(omap->dev);
|
||||
err_disable_pm:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
err_free_mem:
|
||||
|
||||
return r;
|
||||
}
|
||||
|
@ -1530,7 +1530,7 @@ static int omap_i2c_remove(struct platform_device *pdev)
|
|||
int ret;
|
||||
|
||||
i2c_del_adapter(&omap->adapter);
|
||||
ret = pm_runtime_get_sync(&pdev->dev);
|
||||
ret = pm_runtime_resume_and_get(&pdev->dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
|
@ -471,7 +471,10 @@ static int sh7760_i2c_probe(struct platform_device *pdev)
|
|||
goto out2;
|
||||
}
|
||||
|
||||
id->irq = platform_get_irq(pdev, 0);
|
||||
ret = platform_get_irq(pdev, 0);
|
||||
if (ret < 0)
|
||||
goto out3;
|
||||
id->irq = ret;
|
||||
|
||||
id->adap.nr = pdev->id;
|
||||
id->adap.algo = &sh7760_i2c_algo;
|
||||
|
|
|
@ -290,7 +290,7 @@ static int sprd_i2c_master_xfer(struct i2c_adapter *i2c_adap,
|
|||
struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
|
||||
int im, ret;
|
||||
|
||||
ret = pm_runtime_get_sync(i2c_dev->dev);
|
||||
ret = pm_runtime_resume_and_get(i2c_dev->dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
@ -577,7 +577,7 @@ static int sprd_i2c_remove(struct platform_device *pdev)
|
|||
struct sprd_i2c *i2c_dev = platform_get_drvdata(pdev);
|
||||
int ret;
|
||||
|
||||
ret = pm_runtime_get_sync(i2c_dev->dev);
|
||||
ret = pm_runtime_resume_and_get(i2c_dev->dev);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
|
|
@ -2492,7 +2492,7 @@ int i3c_master_register(struct i3c_master_controller *master,
|
|||
|
||||
ret = i3c_master_bus_init(master);
|
||||
if (ret)
|
||||
goto err_destroy_wq;
|
||||
goto err_put_dev;
|
||||
|
||||
ret = device_add(&master->dev);
|
||||
if (ret)
|
||||
|
@ -2523,9 +2523,6 @@ err_del_dev:
|
|||
err_cleanup_bus:
|
||||
i3c_master_bus_cleanup(master);
|
||||
|
||||
err_destroy_wq:
|
||||
destroy_workqueue(master->wq);
|
||||
|
||||
err_put_dev:
|
||||
put_device(&master->dev);
|
||||
|
||||
|
|
|
@ -215,7 +215,7 @@ static const struct iio_chan_spec adis16201_channels[] = {
|
|||
ADIS_AUX_ADC_CHAN(ADIS16201_AUX_ADC_REG, ADIS16201_SCAN_AUX_ADC, 0, 12),
|
||||
ADIS_INCLI_CHAN(X, ADIS16201_XINCL_OUT_REG, ADIS16201_SCAN_INCLI_X,
|
||||
BIT(IIO_CHAN_INFO_CALIBBIAS), 0, 14),
|
||||
ADIS_INCLI_CHAN(X, ADIS16201_YINCL_OUT_REG, ADIS16201_SCAN_INCLI_Y,
|
||||
ADIS_INCLI_CHAN(Y, ADIS16201_YINCL_OUT_REG, ADIS16201_SCAN_INCLI_Y,
|
||||
BIT(IIO_CHAN_INFO_CALIBBIAS), 0, 14),
|
||||
IIO_CHAN_SOFT_TIMESTAMP(7)
|
||||
};
|
||||
|
|
|
@ -736,6 +736,7 @@ static int bnxt_qplib_alloc_dpi_tbl(struct bnxt_qplib_res *res,
|
|||
|
||||
unmap_io:
|
||||
pci_iounmap(res->pdev, dpit->dbr_bar_reg_iomem);
|
||||
dpit->dbr_bar_reg_iomem = NULL;
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
|
|
|
@ -216,7 +216,7 @@ u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx)
|
|||
goto out;
|
||||
entry->qid = qid;
|
||||
list_add_tail(&entry->entry, &uctx->cqids);
|
||||
for (i = qid; i & rdev->qpmask; i++) {
|
||||
for (i = qid + 1; i & rdev->qpmask; i++) {
|
||||
entry = kmalloc(sizeof(*entry), GFP_KERNEL);
|
||||
if (!entry)
|
||||
goto out;
|
||||
|
|
|
@ -1924,6 +1924,7 @@ int parse_platform_config(struct hfi1_devdata *dd)
|
|||
dd_dev_err(dd, "%s: Failed CRC check at offset %ld\n",
|
||||
__func__, (ptr -
|
||||
(u32 *)dd->platform_config.data));
|
||||
ret = -EINVAL;
|
||||
goto bail;
|
||||
}
|
||||
/* Jump the CRC DWORD */
|
||||
|
|
|
@ -392,12 +392,9 @@ static enum i40iw_status_code add_pble_pool(struct i40iw_sc_dev *dev,
|
|||
i40iw_debug(dev, I40IW_DEBUG_PBLE, "next_fpm_addr = %llx chunk_size[%u] = 0x%x\n",
|
||||
pble_rsrc->next_fpm_addr, chunk->size, chunk->size);
|
||||
pble_rsrc->unallocated_pble -= (chunk->size >> 3);
|
||||
list_add(&chunk->list, &pble_rsrc->pinfo.clist);
|
||||
sd_reg_val = (sd_entry_type == I40IW_SD_TYPE_PAGED) ?
|
||||
sd_entry->u.pd_table.pd_page_addr.pa : sd_entry->u.bp.addr.pa;
|
||||
if (sd_entry->valid)
|
||||
return 0;
|
||||
if (dev->is_pf) {
|
||||
if (dev->is_pf && !sd_entry->valid) {
|
||||
ret_code = i40iw_hmc_sd_one(dev, hmc_info->hmc_fn_id,
|
||||
sd_reg_val, idx->sd_idx,
|
||||
sd_entry->entry_type, true);
|
||||
|
@ -408,6 +405,7 @@ static enum i40iw_status_code add_pble_pool(struct i40iw_sc_dev *dev,
|
|||
}
|
||||
|
||||
sd_entry->valid = true;
|
||||
list_add(&chunk->list, &pble_rsrc->pinfo.clist);
|
||||
return 0;
|
||||
error:
|
||||
kfree(chunk);
|
||||
|
|
|
@ -636,8 +636,10 @@ int qedr_iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param)
|
|||
memcpy(in_params.local_mac_addr, dev->ndev->dev_addr, ETH_ALEN);
|
||||
|
||||
if (test_and_set_bit(QEDR_IWARP_CM_WAIT_FOR_CONNECT,
|
||||
&qp->iwarp_cm_flags))
|
||||
&qp->iwarp_cm_flags)) {
|
||||
rc = -ENODEV;
|
||||
goto err; /* QP already being destroyed */
|
||||
}
|
||||
|
||||
rc = dev->ops->iwarp_connect(dev->rdma_ctx, &in_params, &out_params);
|
||||
if (rc) {
|
||||
|
|
|
@ -106,8 +106,6 @@ int siw_mr_add_mem(struct siw_mr *mr, struct ib_pd *pd, void *mem_obj,
|
|||
mem->perms = rights & IWARP_ACCESS_MASK;
|
||||
kref_init(&mem->ref);
|
||||
|
||||
mr->mem = mem;
|
||||
|
||||
get_random_bytes(&next, 4);
|
||||
next &= 0x00ffffff;
|
||||
|
||||
|
@ -116,6 +114,8 @@ int siw_mr_add_mem(struct siw_mr *mr, struct ib_pd *pd, void *mem_obj,
|
|||
kfree(mem);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
mr->mem = mem;
|
||||
/* Set the STag index part */
|
||||
mem->stag = id << 8;
|
||||
mr->base_mr.lkey = mr->base_mr.rkey = mem->stag;
|
||||
|
|
|
@ -2373,6 +2373,7 @@ static int srpt_cm_req_recv(struct srpt_device *const sdev,
|
|||
pr_info("rejected SRP_LOGIN_REQ because target %s_%d is not enabled\n",
|
||||
dev_name(&sdev->device->dev), port_num);
|
||||
mutex_unlock(&sport->mutex);
|
||||
ret = -EINVAL;
|
||||
goto reject;
|
||||
}
|
||||
|
||||
|
|
|
@ -303,7 +303,7 @@ int __init mbi_init(struct fwnode_handle *fwnode, struct irq_domain *parent)
|
|||
reg = of_get_property(np, "mbi-alias", NULL);
|
||||
if (reg) {
|
||||
mbi_phys_base = of_translate_address(np, reg);
|
||||
if (mbi_phys_base == OF_BAD_ADDR) {
|
||||
if (mbi_phys_base == (phys_addr_t)OF_BAD_ADDR) {
|
||||
ret = -ENXIO;
|
||||
goto err_free_mbi;
|
||||
}
|
||||
|
|
|
@ -1726,6 +1726,8 @@ void md_bitmap_flush(struct mddev *mddev)
|
|||
md_bitmap_daemon_work(mddev);
|
||||
bitmap->daemon_lastrun -= sleep;
|
||||
md_bitmap_daemon_work(mddev);
|
||||
if (mddev->bitmap_info.external)
|
||||
md_super_wait(mddev);
|
||||
md_bitmap_update_sb(bitmap);
|
||||
}
|
||||
|
||||
|
|
|
@ -647,7 +647,34 @@ void mddev_init(struct mddev *mddev)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(mddev_init);
|
||||
|
||||
static struct mddev *mddev_find_locked(dev_t unit)
|
||||
{
|
||||
struct mddev *mddev;
|
||||
|
||||
list_for_each_entry(mddev, &all_mddevs, all_mddevs)
|
||||
if (mddev->unit == unit)
|
||||
return mddev;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static struct mddev *mddev_find(dev_t unit)
|
||||
{
|
||||
struct mddev *mddev;
|
||||
|
||||
if (MAJOR(unit) != MD_MAJOR)
|
||||
unit &= ~((1 << MdpMinorShift) - 1);
|
||||
|
||||
spin_lock(&all_mddevs_lock);
|
||||
mddev = mddev_find_locked(unit);
|
||||
if (mddev)
|
||||
mddev_get(mddev);
|
||||
spin_unlock(&all_mddevs_lock);
|
||||
|
||||
return mddev;
|
||||
}
|
||||
|
||||
static struct mddev *mddev_find_or_alloc(dev_t unit)
|
||||
{
|
||||
struct mddev *mddev, *new = NULL;
|
||||
|
||||
|
@ -658,13 +685,13 @@ static struct mddev *mddev_find(dev_t unit)
|
|||
spin_lock(&all_mddevs_lock);
|
||||
|
||||
if (unit) {
|
||||
list_for_each_entry(mddev, &all_mddevs, all_mddevs)
|
||||
if (mddev->unit == unit) {
|
||||
mddev_get(mddev);
|
||||
spin_unlock(&all_mddevs_lock);
|
||||
kfree(new);
|
||||
return mddev;
|
||||
}
|
||||
mddev = mddev_find_locked(unit);
|
||||
if (mddev) {
|
||||
mddev_get(mddev);
|
||||
spin_unlock(&all_mddevs_lock);
|
||||
kfree(new);
|
||||
return mddev;
|
||||
}
|
||||
|
||||
if (new) {
|
||||
list_add(&new->all_mddevs, &all_mddevs);
|
||||
|
@ -690,12 +717,7 @@ static struct mddev *mddev_find(dev_t unit)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
is_free = 1;
|
||||
list_for_each_entry(mddev, &all_mddevs, all_mddevs)
|
||||
if (mddev->unit == dev) {
|
||||
is_free = 0;
|
||||
break;
|
||||
}
|
||||
is_free = !mddev_find_locked(dev);
|
||||
}
|
||||
new->unit = dev;
|
||||
new->md_minor = MINOR(dev);
|
||||
|
@ -5436,7 +5458,7 @@ static int md_alloc(dev_t dev, char *name)
|
|||
* writing to /sys/module/md_mod/parameters/new_array.
|
||||
*/
|
||||
static DEFINE_MUTEX(disks_mutex);
|
||||
struct mddev *mddev = mddev_find(dev);
|
||||
struct mddev *mddev = mddev_find_or_alloc(dev);
|
||||
struct gendisk *disk;
|
||||
int partitioned;
|
||||
int shift;
|
||||
|
@ -6312,11 +6334,9 @@ static void autorun_devices(int part)
|
|||
|
||||
md_probe(dev, NULL, NULL);
|
||||
mddev = mddev_find(dev);
|
||||
if (!mddev || !mddev->gendisk) {
|
||||
if (mddev)
|
||||
mddev_put(mddev);
|
||||
if (!mddev)
|
||||
break;
|
||||
}
|
||||
|
||||
if (mddev_lock(mddev))
|
||||
pr_warn("md: %s locked, cannot run\n", mdname(mddev));
|
||||
else if (mddev->raid_disks || mddev->major_version
|
||||
|
@ -7618,8 +7638,7 @@ static int md_open(struct block_device *bdev, fmode_t mode)
|
|||
/* Wait until bdev->bd_disk is definitely gone */
|
||||
if (work_pending(&mddev->del_work))
|
||||
flush_workqueue(md_misc_wq);
|
||||
/* Then retry the open from the top */
|
||||
return -ERESTARTSYS;
|
||||
return -EBUSY;
|
||||
}
|
||||
BUG_ON(mddev != bdev->bd_disk->private_data);
|
||||
|
||||
|
@ -7952,7 +7971,11 @@ static void *md_seq_start(struct seq_file *seq, loff_t *pos)
|
|||
loff_t l = *pos;
|
||||
struct mddev *mddev;
|
||||
|
||||
if (l >= 0x10000)
|
||||
if (l == 0x10000) {
|
||||
++*pos;
|
||||
return (void *)2;
|
||||
}
|
||||
if (l > 0x10000)
|
||||
return NULL;
|
||||
if (!l--)
|
||||
/* header */
|
||||
|
@ -9049,11 +9072,11 @@ void md_check_recovery(struct mddev *mddev)
|
|||
}
|
||||
|
||||
if (mddev_is_clustered(mddev)) {
|
||||
struct md_rdev *rdev;
|
||||
struct md_rdev *rdev, *tmp;
|
||||
/* kick the device if another node issued a
|
||||
* remove disk.
|
||||
*/
|
||||
rdev_for_each(rdev, mddev) {
|
||||
rdev_for_each_safe(rdev, tmp, mddev) {
|
||||
if (test_and_clear_bit(ClusterRemove, &rdev->flags) &&
|
||||
rdev->raid_disk < 0)
|
||||
md_kick_rdev_from_array(rdev);
|
||||
|
@ -9366,7 +9389,7 @@ err_wq:
|
|||
static void check_sb_changes(struct mddev *mddev, struct md_rdev *rdev)
|
||||
{
|
||||
struct mdp_superblock_1 *sb = page_address(rdev->sb_page);
|
||||
struct md_rdev *rdev2;
|
||||
struct md_rdev *rdev2, *tmp;
|
||||
int role, ret;
|
||||
char b[BDEVNAME_SIZE];
|
||||
|
||||
|
@ -9383,7 +9406,7 @@ static void check_sb_changes(struct mddev *mddev, struct md_rdev *rdev)
|
|||
}
|
||||
|
||||
/* Check for change of roles in the active devices */
|
||||
rdev_for_each(rdev2, mddev) {
|
||||
rdev_for_each_safe(rdev2, tmp, mddev) {
|
||||
if (test_bit(Faulty, &rdev2->flags))
|
||||
continue;
|
||||
|
||||
|
|
|
@ -491,8 +491,8 @@ static void aspeed_video_off(struct aspeed_video *video)
|
|||
aspeed_video_write(video, VE_INTERRUPT_STATUS, 0xffffffff);
|
||||
|
||||
/* Turn off the relevant clocks */
|
||||
clk_disable(video->vclk);
|
||||
clk_disable(video->eclk);
|
||||
clk_disable(video->vclk);
|
||||
|
||||
clear_bit(VIDEO_CLOCKS_ON, &video->flags);
|
||||
}
|
||||
|
@ -503,8 +503,8 @@ static void aspeed_video_on(struct aspeed_video *video)
|
|||
return;
|
||||
|
||||
/* Turn on the relevant clocks */
|
||||
clk_enable(video->eclk);
|
||||
clk_enable(video->vclk);
|
||||
clk_enable(video->eclk);
|
||||
|
||||
set_bit(VIDEO_CLOCKS_ON, &video->flags);
|
||||
}
|
||||
|
@ -1684,8 +1684,11 @@ static int aspeed_video_probe(struct platform_device *pdev)
|
|||
return rc;
|
||||
|
||||
rc = aspeed_video_setup_video(video);
|
||||
if (rc)
|
||||
if (rc) {
|
||||
clk_unprepare(video->vclk);
|
||||
clk_unprepare(video->eclk);
|
||||
return rc;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -151,8 +151,10 @@ static int sun6i_video_start_streaming(struct vb2_queue *vq, unsigned int count)
|
|||
}
|
||||
|
||||
subdev = sun6i_video_remote_subdev(video, NULL);
|
||||
if (!subdev)
|
||||
if (!subdev) {
|
||||
ret = -EINVAL;
|
||||
goto stop_media_pipeline;
|
||||
}
|
||||
|
||||
config.pixelformat = video->fmt.fmt.pix.pixelformat;
|
||||
config.code = video->mbus_code;
|
||||
|
|
|
@ -1025,7 +1025,7 @@ int vivid_vid_out_s_fbuf(struct file *file, void *fh,
|
|||
return -EINVAL;
|
||||
}
|
||||
dev->fbuf_out_flags &= ~(chroma_flags | alpha_flags);
|
||||
dev->fbuf_out_flags = a->flags & (chroma_flags | alpha_flags);
|
||||
dev->fbuf_out_flags |= a->flags & (chroma_flags | alpha_flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -525,7 +525,7 @@ static int m88rs6000t_get_rf_strength(struct dvb_frontend *fe, u16 *strength)
|
|||
PGA2_cri = PGA2_GC >> 2;
|
||||
PGA2_crf = PGA2_GC & 0x03;
|
||||
|
||||
for (i = 0; i <= RF_GC; i++)
|
||||
for (i = 0; i <= RF_GC && i < ARRAY_SIZE(RFGS); i++)
|
||||
RFG += RFGS[i];
|
||||
|
||||
if (RF_GC == 0)
|
||||
|
@ -537,12 +537,12 @@ static int m88rs6000t_get_rf_strength(struct dvb_frontend *fe, u16 *strength)
|
|||
if (RF_GC == 3)
|
||||
RFG += 100;
|
||||
|
||||
for (i = 0; i <= IF_GC; i++)
|
||||
for (i = 0; i <= IF_GC && i < ARRAY_SIZE(IFGS); i++)
|
||||
IFG += IFGS[i];
|
||||
|
||||
TIAG = TIA_GC * TIA_GS;
|
||||
|
||||
for (i = 0; i <= BB_GC; i++)
|
||||
for (i = 0; i <= BB_GC && i < ARRAY_SIZE(BBGS); i++)
|
||||
BBG += BBGS[i];
|
||||
|
||||
PGA2G = PGA2_cri * PGA2_cri_GS + PGA2_crf * PGA2_crf_GS;
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue