PCI/ACPI: Add Ampere Altra SOC MCFG quirk
commit 877c1a5f79c6984bbe3f2924234c08e2f4f1acd5 upstream. Ampere Altra SOC supports only 32-bit ECAM reads. Add an MCFG quirk for the platform. Link: https://lore.kernel.org/r/1596751055-12316-1-git-send-email-tuanphan@os.amperecomputing.com Signed-off-by: Tuan Phan <tuanphan@os.amperecomputing.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> [ dannf: backport drops const qualifier from pci_32b_read_ops for consistency with the other quirks that weren't yet constified in v5.4 ] Signed-off-by: dann frazier <dann.frazier@canonical.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -142,6 +142,26 @@ static struct mcfg_fixup mcfg_quirks[] = {
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XGENE_V2_ECAM_MCFG(4, 0),
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XGENE_V2_ECAM_MCFG(4, 0),
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XGENE_V2_ECAM_MCFG(4, 1),
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XGENE_V2_ECAM_MCFG(4, 1),
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XGENE_V2_ECAM_MCFG(4, 2),
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XGENE_V2_ECAM_MCFG(4, 2),
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#define ALTRA_ECAM_QUIRK(rev, seg) \
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{ "Ampere", "Altra ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops }
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ALTRA_ECAM_QUIRK(1, 0),
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ALTRA_ECAM_QUIRK(1, 1),
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ALTRA_ECAM_QUIRK(1, 2),
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ALTRA_ECAM_QUIRK(1, 3),
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ALTRA_ECAM_QUIRK(1, 4),
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ALTRA_ECAM_QUIRK(1, 5),
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ALTRA_ECAM_QUIRK(1, 6),
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ALTRA_ECAM_QUIRK(1, 7),
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ALTRA_ECAM_QUIRK(1, 8),
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ALTRA_ECAM_QUIRK(1, 9),
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ALTRA_ECAM_QUIRK(1, 10),
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ALTRA_ECAM_QUIRK(1, 11),
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ALTRA_ECAM_QUIRK(1, 12),
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ALTRA_ECAM_QUIRK(1, 13),
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ALTRA_ECAM_QUIRK(1, 14),
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ALTRA_ECAM_QUIRK(1, 15),
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};
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};
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static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
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static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
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@ -164,4 +164,14 @@ struct pci_ecam_ops pci_32b_ops = {
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.write = pci_generic_config_write32,
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.write = pci_generic_config_write32,
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}
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}
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};
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};
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/* ECAM ops for 32-bit read only (non-compliant) */
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struct pci_ecam_ops pci_32b_read_ops = {
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.bus_shift = 20,
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.pci_ops = {
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.map_bus = pci_ecam_map_bus,
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.read = pci_generic_config_read32,
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.write = pci_generic_config_write,
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}
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};
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#endif
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#endif
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@ -51,6 +51,7 @@ extern struct pci_ecam_ops pci_generic_ecam_ops;
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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extern struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
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extern struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
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extern struct pci_ecam_ops pci_32b_read_ops; /* 32-bit read only */
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extern struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */
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extern struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */
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extern struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */
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extern struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */
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extern struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */
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extern struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */
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