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ARM: dts: imx7ulp: Add OPP table for cpu0

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Add OPP table for cpu0 to support i.MX7ULP cpufreq.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
This commit is contained in:
Anson Huang 2019-08-08 08:08:30 +08:00 committed by Dong Aisheng
parent 625e5c3e56
commit 3535a94ea8
2 changed files with 21 additions and 0 deletions
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4
arch/arm/boot/dts/imx7ulp-evk.dts
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@ -176,6 +176,10 @@
};
};
&cpu0 {
arm-supply= <&sw1_reg>;
};
&lpuart4 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_lpuart4>;

17
arch/arm/boot/dts/imx7ulp.dtsi
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@ -41,6 +41,23 @@
compatible = "arm,cortex-a7";
device_type = "cpu";
reg = <0>;
operating-points = <
/* KHz uV */
720000 1125000
500210 1025000
>;
clocks = <&smc1 IMX7ULP_CLK_ARM>,
<&scg1 IMX7ULP_CLK_CORE_DIV>,
<&scg1 IMX7ULP_CLK_SYS_SEL>,
<&scg1 IMX7ULP_CLK_HSRUN_SYS_SEL>,
<&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>,
<&scg1 IMX7ULP_CLK_SPLL_PFD0>,
<&scg1 IMX7ULP_CLK_SPLL_SEL>,
<&scg1 IMX7ULP_CLK_FIRC>,
<&scg1 IMX7ULP_CLK_SPLL>;
clock-names = "arm", "core_div", "sys_sel", "hsrun_sys_sel",
"hsrun_core", "spll_pfd0", "spll_sel", "firc",
"spll";
};
};