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ARM: dts: imx7ulp: Add necessary nodes for suspend/resume support

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Add necessary nodes for suspend/resume support, including wdog
node which is needed for initializing wdog when resumed from
VLLS mode.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
This commit is contained in:
Anson Huang 2019-08-07 18:26:38 +08:00 committed by Dong Aisheng
parent c6d6238d26
commit 625e5c3e56
1 changed files with 47 additions and 0 deletions
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47
arch/arm/boot/dts/imx7ulp.dtsi
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@ -94,6 +94,11 @@
#clock-cells = <0>;
};
sram: sram@20000000 {
compatible = "fsl,lpm-sram";
reg = <0x1fffc000 0x4000>;
};
ahbbridge0: bus@40000000 {
compatible = "simple-bus";
#address-cells = <1>;
@ -136,6 +141,13 @@
#mbox-cells = <2>;
};
nmi: nmi@40220000 {
compatible = "fsl,imx7ulp-nmi";
reg = <0x40220000 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
mu_lp: mu_lp@40220000 {
compatible = "fsl,imx7ulp-mu-lp", "fsl,imx6sx-mu-lp";
reg = <0x40220000 0x1000>;
@ -281,6 +293,31 @@
#clock-cells = <1>;
};
wdog1: wdog@403D0000 {
compatible = "fsl,imx7ulp-wdt";
reg = <0x403D0000 0x10000>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
/*
* As the 1KHz LPO clock rate is not trimed,the actually clock
* is about 667Hz, so the init timeout 60s should set 40*1000
* in the TOVAL register.
*/
timeout-sec = <40>;
};
wdog2: wdog@40430000 {
compatible = "fsl,imx7ulp-wdt";
reg = <0x40430000 0x10000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc2 IMX7ULP_CLK_WDG2>;
assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG2>;
assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
timeout-sec = <40>;
};
pcc2: clock-controller@403f0000 {
compatible = "fsl,imx7ulp-pcc2";
reg = <0x403f0000 0x10000>;
@ -305,6 +342,11 @@
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
};
pmc1: pmc1@40400000 {
compatible = "fsl,imx7ulp-pmc1";
reg = <0x40400000 0x1000>;
};
smc1: clock-controller@40410000 {
compatible = "fsl,imx7ulp-smc1";
reg = <0x40410000 0x1000>;
@ -471,6 +513,11 @@
reg = <0x41080000 0x80000>;
ranges;
pmc0: pmc0@410a1000 {
compatible = "fsl,imx7ulp-pmc0";
reg = <0x410a1000 0x1000>;
};
sim: sim@410a3000 {
compatible = "fsl,imx7ulp-sim", "syscon";
reg = <0x410a3000 0x1000>;