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MLK-25915-2 clk: imx: imx8m: correct the pcie aux sels 

The sys2_pll_50m should be one of the clock sels of PCIE_AUX clock,
otherwise the sys2_pll_500m.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Peter Chen <peter.chen@nxp.com>
(cherry picked from commit 0af1467f5c58229c8220d54d38ce9b6152361387)
(cherry picked from commit 885518850911ae44a351d15a9c12b6d12c431616)
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
This commit is contained in:
Richard Zhu 2020-12-29 14:49:01 +08:00 committed by Andrey Zhizhikin
parent 5a681dc20e
commit 086db5a350
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/imx/clk-imx8mq.c
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@ -123,7 +123,7 @@ static const char * const imx8mq_pcie1_ctrl_sels[] = {"osc_25m", "sys2_pll_250m"
static const char * const imx8mq_pcie1_phy_sels[] = {"osc_25m", "sys2_pll_100m", "sys2_pll_500m", "clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4", };
static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_500m", "sys3_pll_out",
static const char * const imx8mq_pcie1_aux_sels[] = {"osc_25m", "sys2_pll_200m", "sys2_pll_50m", "sys3_pll_out",
"sys2_pll_100m", "sys1_pll_80m", "sys1_pll_160m", "sys1_pll_200m", };
static const char * const imx8mq_dc_pixel_sels[] = {"osc_25m", "video_pll1_out", "audio_pll2_out", "audio_pll1_out", "sys1_pll_800m", "sys2_pll_1000m", "sys3_pll_out", "clk_ext4", };