brain-hackers_pepepper-mirror/linux-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/linux-brain.git synced 2024-06-09 07:16:21 +09:00
Code Issues Projects Releases Wiki Activity

MLK-25915-1 arm64: dts: imx8m: set the parent clock of pcie aux clock

Browse Source 
Set the parent clock for PCIE_AUX clock firstly, then set the rate of
the PCI_AUX clock to 10MHZ.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Peter Chen <peter.chen@nxp.com>
(cherry picked from commit c787efe575330e538cc92da0dde49255bdc80c94)
(cherry picked from commit 855ad0c9b3e9ea03f34c70332a2175cd604acf6c)
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
This commit is contained in:
Richard Zhu 2020-12-29 15:41:35 +08:00 committed by Andrey Zhizhikin
parent a32bd46924
commit 5a681dc20e
3 changed files with 17 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm64/boot/dts/freescale/imx8mm-evk.dts
View File

@ -230,6 +230,9 @@
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>;
ext_osc = <1>;
status = "okay";
};
@ -242,6 +245,9 @@
<&clk IMX8MM_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>;
ext_osc = <1>;
status = "disabled";
};

2
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@ -686,6 +686,7 @@
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>,
<&clk IMX8MP_CLK_PCIE_AUX>;
assigned-clock-rates = <500000000>, <10000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_SYS_PLL2_50M>;
status = "okay";
@ -702,6 +703,7 @@
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>,
<&clk IMX8MP_CLK_PCIE_AUX>;
assigned-clock-rates = <500000000>, <10000000>;
assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
<&clk IMX8MP_SYS_PLL2_50M>;
status = "disabled";

9
arch/arm64/boot/dts/freescale/imx8mq-evk.dts
View File

@ -662,6 +662,9 @@
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>;
hard-wired = <1>;
status = "okay";
};
@ -676,6 +679,9 @@
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>;
status = "okay";
};
@ -687,6 +693,9 @@
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_AUX>;
assigned-clock-rates = <10000000>;
assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_50M>;
status = "disabled";
};