lab/x1/injector/disable_mmu.S
2021-06-28 15:28:06 +09:00

98 lines
3.1 KiB
ArmAsm
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.text
.align 2
.global _start
_start:
//preload U-Boot from sd
ldr r4, .L3
adr r1, [.LC0]
adr r0, [.LC1]
mov r3, r4
blx r3
add r5, r4, #0xc
mov r3, r0
ldr r0, .L3+4
mov r1, #1
mov r2, r0
blx r5
cpsid if
//copy U-Boot to head of RAM
ldr r3, =0x37500000
ldr r1, =0x37540000
.L2:
mov r2, r3
sub r3, r3, #0x7500000
ldr r0, [r2], #4
cmp r2, r1
str r0, [r3]
mov r3, r2
bne .L2
ldr r0, =0x60000000
//MUB Interrupt Disable
ldr r2,=0x40220064
ldr r3,[r2]
ldr r1,=0x0000ffff
and r3,r3,r1
str r3,[r2]
mrc p15, 0, r8, c14, c2, 1
bic r8, r8, #1
mcr p15, 0, r8, c14, c2, 1
mrc p15, 0, r8, c14, c3, 1
bic r8, r8, #1
mcr p15, 0, r8, c14, c3, 1
mov r9, #0
mrc p15, 0, r6, c1, c0, 0
bic r6, r6, #4 @ disable dcache
bic r6, r6, #4096 @ disable icache
mcr p15, 0, r6, c1, c0, 0 // write ctrl regs
mcr p15, 0, r9, c7, c5, 0 // invalidate icache
// from: https://www.aps-web.jp/academy/ca/229/#i-2
mov r10,#0 //
mcr p15,2,r10,c0,c0,0 // CSSELR
//
isb //
mrc p15,1,r1,c0,c0,0 // CCSIDR
and r2,r1,#7 // b001=8ワード/
add r2,r2,#4 // DCISW
ldr r4,=0x3FF //
ands r4,r4,r1,LSR #3 // r4
clz r5,r4 // DCISW
ldr r7,=0x7FFF //
ands r7,r7,r1,LSR #13 // r7
// 0x7F=12Kbyte/0xFF=32Kbyte/0x1FF=64Kbyte
loop2:
mov r9,r4 // r9
loop3:
orr r11,r10,r9,LSL r5 //
orr r11,r11,r7,LSL r2 //
mcr p15,0,r11,c7,c6,2 // DCISW/
//
subs r9,r9,#1 // -1
bge loop3 //
subs r7,r7,#1 // -1
bge loop2 //
mcr p15, 0, r9, c8, c7, 0 // invalidate TLB
mcr p15, 0, r9, c7, c5, 6 // invalidate branch predictor array
bic r6, r6, #1 @ disable MMU
mcr p15, 0, r6, c1, c0, 0 // write ctrl regs
bx r0
.L3:
.word 0x60006400
.word 0x37500000
.LC0:
.ascii "r\000"
.LC1:
.ascii "SD0:\\u-boot.bin\000"