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5 Commits
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cbf1b89241
Author | SHA1 | Date |
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Chiharu Shirasaka | cbf1b89241 | |
Chiharu Shirasaka | 0a091e3515 | |
Chiharu Shirasaka | 3de439eb6f | |
Chiharu Shirasaka | 17cc2d2278 | |
Chiharu Shirasaka | 3744630abf |
6
Makefile
6
Makefile
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@ -4,7 +4,7 @@ CC:=$(CROSS_COMPILE)gcc
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STRIP:=$(CROSS_COMPILE)strip
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.PHONY:
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all: AppMain.bin
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all: AppMain.bin m4_loader.bin
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.PHONY:
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clean:
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@ -13,3 +13,7 @@ clean:
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AppMain.bin:
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@$(AS) main.S -o main.elf
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@./extract.py -p main.elf AppMain.bin
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m4_loader.bin:
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@$(AS) m4_loader.S -mcpu=cortex-m4 -o m4_loader.elf
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@./extract.py -p m4_loader.elf m4_loader.bin
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@ -0,0 +1,40 @@
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.text
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.thumb
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.syntax unified
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.align 2
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.global _start
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_start:
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cpsid i
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//LPTMR0 interrupt stop
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ldr r0, =0x4102e000
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eor r1, r1, r1
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str r1, [r0]
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//M4 RTOS loader
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ldr r0, =0x1FFD2000 //M4 SRAM start addr
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ldr r1, =0x67400000 //M4 RTOS preload addr
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ldr r2, =0 //increment register
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ldr r4, [r1, #-4] //M4 RTOS size
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loop:
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ldr r3, [r1, r2] //load from dram
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str r3, [r0, r2] //store to sram
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add r2, #4 //increment
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cmp r2, r4 //does copy end?
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ble loop
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//return address override
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mrs r4, psp
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adr r5, jumper
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orr r5, r5, #1
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str r5, [r4,#24]
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bx lr //exit interrupt handler
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jumper: //M4 RTOS image jumper
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mrs r0, control
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bic r0, #2
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msr control, r0
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isb
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ldr r0, =0x1ffd2000 //M4 RTOS image head addr
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ldr r1, [r0] //initial stack addr
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mov sp, r1
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ldr r2, [r0,#4] //reset vector
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bx r2
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56
main.S
56
main.S
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@ -3,6 +3,54 @@
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.global _start
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_start:
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//M4 RTOS loader snipet prep
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ldr r4, =0x60006400 //fopen addr
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adr r0, [.LC2] //file name
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adr r1, [.LC1] //open mode
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blx r4
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add r5, r4, #0xc //fread addr
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mov r3, r0 //file descriptor
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ldr r0, =0x1ffe4000 //fread destination
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mov r1, #1 //read unit size
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mov r2, r0 //read unit count(over size)
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blx r5
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//M4 RTOS preload
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ldr r4, =0x60006400 //fopen addr
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adr r0, [.LC3] //file name
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adr r1, [.LC1] //open mode
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blx r4
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add r5, r4, #0xc //fread addr
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mov r3, r0 //file descriptor
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ldr r0, =0x37400000 //fread destination
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mov r1, #1 //read unit size
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mov r2, r0 //read unit count(over size)
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blx r5
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//M4 RTOS size get
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ldr r4, =0x60006444 //stat addr
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adr r0, [.LC3] //file name
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sub sp, sp, #0x14
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mov r1, sp
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blx r4
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ldr r0, =0x373ffffc //store size before data
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ldr r1, [sp,#0x10]
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str r1, [r0]
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//M4 interrupt prep
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ldr r4, =0x1ffd20d0 //NVIC MCM vector
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ldr r5, =0x1ffe4001 //loader addr | 0x1(thumb)
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str r5, [r4] //override interrupt handler
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//wait until M4 RTOS copied
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ldr r4, =0x1ffd2000 //get sram img start addr
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add r0, r0, #4 //get dram rtos addr
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ldr r3, [r0, r1] //get last word of rtos on dram
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rtos_loop:
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ldr r2, [r4,r1] //get last word of rtos on sram
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cmp r2,r3
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bne rtos_loop
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//preload U-Boot from sd
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ldr r4, =0x60006400 //fopen addr
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adr r0, [.LC0] //file name
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@ -20,13 +68,17 @@ _start:
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.ascii "SD0:\\u-boot.bin\000"
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.LC1:
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.ascii "r\000"
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.LC2:
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.ascii "SD0:\\m4_loader.bin\000"
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.LC3:
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.ascii "SD0:\\m4_rtos.bin\000"
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.align 4
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continue:
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cpsid if //disable interrupt
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//copy U-Boot to head of RAM
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ldr r3, =0x37500000 //copy start
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ldr r1, =0x37540000 //copy end
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add r1, r3, r0 //copy end
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copy_loop:
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mov r2, r3
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sub r3, r3, #0x7500000 //copy distination
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@ -34,7 +86,7 @@ _start:
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cmp r2, r1
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str r0, [r3]
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mov r3, r2
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bne copy_loop
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blt copy_loop
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//RAM clear
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ldr r2,=0x60200000 //clear start
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