M4 RTOS loader ready

This commit is contained in:
Chiharu Shirasaka 2021-11-30 22:56:47 +09:00 committed by Takumi Sueda
parent 3de439eb6f
commit 0a091e3515
3 changed files with 93 additions and 1 deletions

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@ -4,7 +4,7 @@ CC:=$(CROSS_COMPILE)gcc
STRIP:=$(CROSS_COMPILE)strip
.PHONY:
all: AppMain.bin
all: AppMain.bin m4_loader.bin
.PHONY:
clean:
@ -13,3 +13,7 @@ clean:
AppMain.bin:
@$(AS) main.S -o main.elf
@./extract.py -p main.elf AppMain.bin
m4_loader.bin:
@$(AS) m4_loader.S -mcpu=cortex-m4 -o m4_loader.elf
@./extract.py -p m4_loader.elf m4_loader.bin

36
m4_loader.S Normal file
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@ -0,0 +1,36 @@
.text
.thumb
.syntax unified
.align 2
.global _start
_start:
cpsid i
//M4 RTOS loader
ldr r0, =0x1FFD2000 //M4 SRAM start addr
ldr r1, =0x67400000 //M4 RTOS preload addr
ldr r2, =0 //increment register
ldr r4, [r1, #-4] //M4 RTOS size
loop:
ldr r3, [r1, r2] //load from dram
str r3, [r0, r2] //store to sram
add r2, #4 //increment
cmp r2, r4 //does copy end?
ble loop
//return address override
mrs r4, psp
adr r5, jumper
orr r5, r5, #1
str r5, [r4,#24]
bx lr //exit interrupt handler
jumper: //M4 RTOS image jumper
mrs r0, control
bic r0, #2
msr control, r0
isb
ldr r0, =0x1ffd2000 //M4 RTOS image head addr
ldr r1, [r0] //initial stack addr
mov sp, r1
ldr r2, [r0,#4] //reset vector
bx r2

52
main.S
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@ -3,6 +3,54 @@
.global _start
_start:
//M4 RTOS loader snipet prep
ldr r4, =0x60006400 //fopen addr
adr r0, [.LC2] //file name
adr r1, [.LC1] //open mode
blx r4
add r5, r4, #0xc //fread addr
mov r3, r0 //file descriptor
ldr r0, =0x1ffe4000 //fread destination
mov r1, #1 //read unit size
mov r2, r0 //read unit count(over size)
blx r5
//M4 RTOS preload
ldr r4, =0x60006400 //fopen addr
adr r0, [.LC3] //file name
adr r1, [.LC1] //open mode
blx r4
add r5, r4, #0xc //fread addr
mov r3, r0 //file descriptor
ldr r0, =0x37400000 //fread destination
mov r1, #1 //read unit size
mov r2, r0 //read unit count(over size)
blx r5
//M4 RTOS size get
ldr r4, =0x60006444 //stat addr
adr r0, [.LC3] //file name
sub sp, sp, #0x14
mov r1, sp
blx r4
ldr r0, =0x373ffffc //store size before data
ldr r1, [sp,#0x10]
str r1, [r0]
//M4 interrupt prep
ldr r4, =0x1ffd20d0 //NVIC MCM vector
ldr r5, =0x1ffe4001 //loader addr | 0x1(thumb)
str r5, [r4] //override interrupt handler
//wait until M4 RTOS copied
ldr r4, =0x1ffd2000 //get sram img start addr
add r0, r0, #4 //get dram rtos addr
ldr r3, [r0, r1] //get last word of rtos on dram
rtos_loop:
ldr r2, [r4,r1] //get last word of rtos on sram
cmp r2,r3
bne rtos_loop
//preload U-Boot from sd
ldr r4, =0x60006400 //fopen addr
adr r0, [.LC0] //file name
@ -20,6 +68,10 @@ _start:
.ascii "SD0:\\u-boot.bin\000"
.LC1:
.ascii "r\000"
.LC2:
.ascii "SD0:\\m4_loader.bin\000"
.LC3:
.ascii "SD0:\\m4_rtos.bin\000"
.align 4
continue:
cpsid if //disable interrupt