Bin Meng ffdc71bc09 Revert "riscv: cpu: fu740: clear feature disable CSR" ... This reverts commit bc8bbb77f7. This commit breaks U-Boot booting on SiFive Unleashed board, as there is no such CSR on U54 core. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>		2021-05-14 16:26:20 +08:00
..
ax25	cpu: Rename SPL_CPU_SUPPORT to SPL_CPU	2021-03-27 15:04:31 +13:00
fu540	Revert "riscv: cpu: fu740: clear feature disable CSR"	2021-05-14 16:26:20 +08:00
generic	cpu: Rename SPL_CPU_SUPPORT to SPL_CPU	2021-03-27 15:04:31 +13:00
cpu.c	riscv: cpu: Add callback to init each core	2021-05-05 16:11:22 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Add option to print registers on exception	2020-02-10 14:51:08 +08:00
start.S	riscv: cpu: Add callback to init each core	2021-05-05 16:11:22 +08:00
u-boot-spl.lds	riscv: Add _image_binary_end for SPL	2020-06-04 09:44:08 +08:00
u-boot.lds	riscv: Fix breakage caused by linker relaxation	2020-02-10 14:50:53 +08:00