Akshay Saraswat 234370cab4 Exynos5: clock: Update the equation to calculate PLL output frequency ... According to the latest exynos5 user manual, the equation for calculating PLL output was changed to FOUT= MDIV x FIN/(PDIV x 2^SDIV) earlier it was FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1)) So updating the clock code accordingly. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>		2013-05-21 20:17:30 +09:00
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cpu	Exynos5: clock: Update the equation to calculate PLL output frequency	2013-05-21 20:17:30 +09:00
dts	EXYNOS5: Add device node for DP	2013-03-27 21:23:18 +09:00
imx-common	imx: iomux-v3: Add iomux-mx35.h	2013-05-05 17:55:03 +02:00
include/asm	arm: at91: add at91sam9n12ek board support	2013-05-12 16:40:42 +02:00
lib	lib: consolidate hang()	2013-05-01 16:41:08 -04:00
config.mk	arm: Remove deprecated and now unused NAND SPL	2013-04-12 07:55:08 +02:00