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https://github.com/brain-hackers/u-boot-brain
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445a886d7a
SoC ag101 is the first chip using NDS32 N1213 cpu core. Add header file of device offset support for SoC ag101. Add main function of SoC ag101 based on NDS32 n1213 core. Add lowlevel_init.S and other periphal related code. This version of lowlevel_init.S also replace hardcode value by MARCO defines from the GPL version andesboot for better code quality. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
49 lines
1.4 KiB
ArmAsm
49 lines
1.4 KiB
ArmAsm
/*
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* Copyright (C) 2011 Andes Technology Corporation
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch-ag101/ag101.h>
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.text
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#ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
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.globl turnoff_watchdog
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turnoff_watchdog:
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#define WD_CR 0xC
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#define WD_ENABLE 0x1
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! Turn off the watchdog, according to Faraday FTWDT010 spec
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li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
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lwi $p1, [$p0] ! Get the config of WD
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andi $p1, $p1, 0x1f ! Wipe out useless bits
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li $r0, ~WD_ENABLE
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and $p1, $p1, $r0 ! Set WD disable
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sw $p1, [$p0] ! Write back to WD CR
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! Disable Interrupts by clear GIE in $PSW reg
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setgie.d
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ret
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#endif
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