mirror of
https://github.com/brain-hackers/u-boot-brain
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![Peter Griffin](/assets/img/avatar_default.png)
This is a binding which only exists in U-Boot, but is required to get working serial in U-Boot. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
219 lines
4.9 KiB
Plaintext
219 lines
4.9 KiB
Plaintext
/*
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* dts file for Hisilicon Hi6220 SoC
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*
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* Copyright (C) 2015, Hisilicon Ltd.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/hi6220-clock.h>
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/ {
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compatible = "hisilicon,hi6220";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x3>;
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enable-method = "psci";
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};
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cpu4: cpu@100 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x100>;
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enable-method = "psci";
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};
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cpu5: cpu@101 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x101>;
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enable-method = "psci";
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};
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cpu6: cpu@102 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x102>;
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enable-method = "psci";
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};
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cpu7: cpu@103 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0x0 0x103>;
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enable-method = "psci";
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};
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};
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gic: interrupt-controller@f6801000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
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<0x0 0xf6802000 0 0x2000>, /* GICC */
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<0x0 0xf6804000 0 0x2000>, /* GICH */
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<0x0 0xf6806000 0 0x2000>; /* GICV */
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#address-cells = <0>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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ao_ctrl: ao_ctrl@f7800000 {
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compatible = "hisilicon,hi6220-aoctrl", "syscon";
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reg = <0x0 0xf7800000 0x0 0x2000>;
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#clock-cells = <1>;
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};
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sys_ctrl: sys_ctrl@f7030000 {
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compatible = "hisilicon,hi6220-sysctrl", "syscon";
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reg = <0x0 0xf7030000 0x0 0x2000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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media_ctrl: media_ctrl@f4410000 {
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compatible = "hisilicon,hi6220-mediactrl", "syscon";
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reg = <0x0 0xf4410000 0x0 0x1000>;
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#clock-cells = <1>;
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};
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pm_ctrl: pm_ctrl@f7032000 {
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compatible = "hisilicon,hi6220-pmctrl", "syscon";
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reg = <0x0 0xf7032000 0x0 0x1000>;
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#clock-cells = <1>;
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};
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uart0: uart@f8015000 { /* console */
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xf8015000 0x0 0x1000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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clock = <19200000>;
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clocks = <&ao_ctrl HI6220_UART0_PCLK>,
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<&ao_ctrl HI6220_UART0_PCLK>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart1: uart@f7111000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xf7111000 0x0 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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clock = <19200000>;
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clocks = <&sys_ctrl HI6220_UART1_PCLK>,
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<&sys_ctrl HI6220_UART1_PCLK>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart2: uart@f7112000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xf7112000 0x0 0x1000>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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clock = <19200000>;
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clocks = <&sys_ctrl HI6220_UART2_PCLK>,
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<&sys_ctrl HI6220_UART2_PCLK>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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uart3: uart@f7113000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xf7113000 0x0 0x1000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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clock = <19200000>;
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clocks = <&sys_ctrl HI6220_UART3_PCLK>,
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<&sys_ctrl HI6220_UART3_PCLK>;
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clock-names = "uartclk", "apb_pclk";
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};
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uart4: uart@f7114000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0xf7114000 0x0 0x1000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clock = <19200000>;
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clocks = <&sys_ctrl HI6220_UART4_PCLK>,
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<&sys_ctrl HI6220_UART4_PCLK>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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};
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};
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