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https://github.com/brain-hackers/u-boot-brain
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a89441a74f
The socfpga gen5 SPL manually zeroed bss in board_init_f(). Now that the DDR driver does not use bss any more, bss is not used before board_init_r() and we can remove this hack. bss is normally zeroed by crt0.S, but after board_init_f(), before board_init_r(). socfpga just had this double-zeroing because it invalidly used bss in board_init_f() already (during DDR initialization). Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> |
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| .. | ||
| include/mach | ||
| board.c | ||
| clock_manager_arria10.c | ||
| clock_manager_gen5.c | ||
| clock_manager_s10.c | ||
| clock_manager.c | ||
| fpga_manager.c | ||
| freeze_controller.c | ||
| Kconfig | ||
| mailbox_s10.c | ||
| Makefile | ||
| misc_arria10.c | ||
| misc_gen5.c | ||
| misc_s10.c | ||
| misc.c | ||
| mmu-arm64_s10.c | ||
| pinmux_arria10.c | ||
| qts-filter.sh | ||
| reset_manager_arria10.c | ||
| reset_manager_gen5.c | ||
| reset_manager_s10.c | ||
| scan_manager.c | ||
| spl_a10.c | ||
| spl_gen5.c | ||
| spl_s10.c | ||
| system_manager_gen5.c | ||
| system_manager_s10.c | ||
| timer_s10.c | ||
| timer.c | ||
| wrap_iocsr_config.c | ||
| wrap_pinmux_config_s10.c | ||
| wrap_pinmux_config.c | ||
| wrap_pll_config_s10.c | ||
| wrap_pll_config.c | ||
| wrap_sdram_config.c | ||