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https://github.com/brain-hackers/u-boot-brain
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![Michal Simek](/assets/img/avatar_default.png)
cpu_cmd() is reading cpu number via simple_strtoul() which is always unsigned type. Platform code implementations are not expecting that nr can be negative and there is not checking in the code for that too. This patch is using u32 type for cpu number to make sure that platform code get proper value range. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
472 lines
11 KiB
C
472 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <ioports.h>
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#include <lmb.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/fsl_law.h>
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#include <fsl_ddr_sdram.h>
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#include "mp.h"
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DECLARE_GLOBAL_DATA_PTR;
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u32 fsl_ddr_get_intl3r(void);
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extern u32 __spin_table[];
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u32 get_my_id()
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{
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return mfspr(SPRN_PIR);
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}
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/*
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* Determine if U-Boot should keep secondary cores in reset, or let them out
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* of reset and hold them in a spinloop
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*/
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int hold_cores_in_reset(int verbose)
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{
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/* Default to no, overridden by 'y', 'yes', 'Y', 'Yes', or '1' */
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if (env_get_yesno("mp_holdoff") == 1) {
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if (verbose) {
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puts("Secondary cores are being held in reset.\n");
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puts("See 'mp_holdoff' environment variable\n");
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}
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return 1;
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}
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return 0;
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}
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int cpu_reset(u32 nr)
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{
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volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
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out_be32(&pic->pir, 1 << nr);
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/* the dummy read works around an errata on early 85xx MP PICs */
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(void)in_be32(&pic->pir);
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out_be32(&pic->pir, 0x0);
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return 0;
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}
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int cpu_status(u32 nr)
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{
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u32 *table, id = get_my_id();
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if (hold_cores_in_reset(1))
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return 0;
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if (nr == id) {
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table = (u32 *)&__spin_table;
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printf("table base @ 0x%p\n", table);
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} else if (is_core_disabled(nr)) {
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puts("Disabled\n");
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} else {
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table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
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printf("Running on cpu %d\n", id);
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printf("\n");
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printf("table @ 0x%p\n", table);
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printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
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printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
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printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
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}
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return 0;
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}
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#ifdef CONFIG_FSL_CORENET
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int cpu_disable(u32 nr)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->coredisrl, 1 << nr);
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return 0;
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}
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int is_core_disabled(int nr) {
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 coredisrl = in_be32(&gur->coredisrl);
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return (coredisrl & (1 << nr));
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}
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#else
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int cpu_disable(u32 nr)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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switch (nr) {
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case 0:
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU0);
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break;
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case 1:
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_CPU1);
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break;
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default:
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printf("Invalid cpu number for disable %d\n", nr);
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return 1;
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}
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return 0;
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}
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int is_core_disabled(int nr) {
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 devdisr = in_be32(&gur->devdisr);
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switch (nr) {
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case 0:
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return (devdisr & MPC85xx_DEVDISR_CPU0);
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case 1:
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return (devdisr & MPC85xx_DEVDISR_CPU1);
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default:
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printf("Invalid cpu number for disable %d\n", nr);
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}
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return 0;
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}
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#endif
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static u8 boot_entry_map[4] = {
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0,
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BOOT_ENTRY_PIR,
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BOOT_ENTRY_R3_LOWER,
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};
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int cpu_release(u32 nr, int argc, char * const argv[])
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{
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u32 i, val, *table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY;
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u64 boot_addr;
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if (hold_cores_in_reset(1))
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return 0;
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if (nr == get_my_id()) {
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printf("Invalid to release the boot core.\n\n");
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return 1;
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}
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if (argc != 4) {
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printf("Invalid number of arguments to release.\n\n");
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return 1;
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}
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boot_addr = simple_strtoull(argv[0], NULL, 16);
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/* handle pir, r3 */
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for (i = 1; i < 3; i++) {
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if (argv[i][0] != '-') {
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u8 entry = boot_entry_map[i];
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val = simple_strtoul(argv[i], NULL, 16);
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table[entry] = val;
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}
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}
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table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
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/* ensure all table updates complete before final address write */
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eieio();
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table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
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return 0;
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}
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u32 determine_mp_bootpg(unsigned int *pagesize)
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{
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u32 bootpg;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
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u32 svr = get_svr();
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u32 granule_size, check;
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struct law_entry e;
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#endif
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/* use last 4K of mapped memory */
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bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
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CONFIG_MAX_MEM_MAPPED : gd->ram_size) +
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CONFIG_SYS_SDRAM_BASE - 4096;
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if (pagesize)
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*pagesize = 4096;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
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/*
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* Erratum A004468 has two parts. The 3-way interleaving applies to T4240,
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* to be fixed in rev 2.0. The 2-way interleaving applies to many SoCs. But
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* the way boot page chosen in u-boot avoids hitting this erratum. So only
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* thw workaround for 3-way interleaving is needed.
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*
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* To make sure boot page translation works with 3-Way DDR interleaving
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* enforce a check for the following constrains
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* 8K granule size requires BRSIZE=8K and
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* bootpg >> log2(BRSIZE) %3 == 1
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* 4K and 1K granule size requires BRSIZE=4K and
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* bootpg >> log2(BRSIZE) %3 == 0
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*/
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if (SVR_SOC_VER(svr) == SVR_T4240 && SVR_MAJ(svr) < 2) {
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e = find_law(bootpg);
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switch (e.trgt_id) {
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case LAW_TRGT_IF_DDR_INTLV_123:
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granule_size = fsl_ddr_get_intl3r() & 0x1f;
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if (granule_size == FSL_DDR_3WAY_8KB_INTERLEAVING) {
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if (pagesize)
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*pagesize = 8192;
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bootpg &= 0xffffe000; /* align to 8KB */
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check = bootpg >> 13;
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while ((check % 3) != 1)
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check--;
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bootpg = check << 13;
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debug("Boot page (8K) at 0x%08x\n", bootpg);
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break;
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} else {
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bootpg &= 0xfffff000; /* align to 4KB */
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check = bootpg >> 12;
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while ((check % 3) != 0)
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check--;
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bootpg = check << 12;
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debug("Boot page (4K) at 0x%08x\n", bootpg);
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}
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break;
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default:
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break;
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}
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}
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#endif /* CONFIG_SYS_FSL_ERRATUM_A004468 */
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return bootpg;
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}
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phys_addr_t get_spin_phys_addr(void)
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{
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return virt_to_phys(&__spin_table);
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}
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#ifdef CONFIG_FSL_CORENET
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static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
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{
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u32 cpu_up_mask, whoami, brsize = LAW_SIZE_4K;
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u32 *table = (u32 *)&__spin_table;
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volatile ccsr_gur_t *gur;
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volatile ccsr_local_t *ccm;
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volatile ccsr_rcpm_t *rcpm;
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volatile ccsr_pic_t *pic;
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int timeout = 10;
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u32 mask = cpu_mask();
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struct law_entry e;
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gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
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rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
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pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
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whoami = in_be32(&pic->whoami);
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cpu_up_mask = 1 << whoami;
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out_be32(&ccm->bstrl, bootpg);
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e = find_law(bootpg);
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/* pagesize is only 4K or 8K */
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if (pagesize == 8192)
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brsize = LAW_SIZE_8K;
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out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | brsize);
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debug("BRSIZE is 0x%x\n", brsize);
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/* readback to sync write */
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in_be32(&ccm->bstrar);
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/* disable time base at the platform */
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out_be32(&rcpm->ctbenrl, cpu_up_mask);
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out_be32(&gur->brrl, mask);
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/* wait for everyone */
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while (timeout) {
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unsigned int i, cpu, nr_cpus = cpu_numcores();
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for_each_cpu(i, cpu, nr_cpus, mask) {
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if (table[cpu * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
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cpu_up_mask |= (1 << cpu);
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}
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if ((cpu_up_mask & mask) == mask)
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break;
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udelay(100);
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timeout--;
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}
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if (timeout == 0)
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printf("CPU up timeout. CPU up mask is %x should be %x\n",
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cpu_up_mask, mask);
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/* enable time base at the platform */
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out_be32(&rcpm->ctbenrl, 0);
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/* readback to sync write */
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in_be32(&rcpm->ctbenrl);
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mtspr(SPRN_TBWU, 0);
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mtspr(SPRN_TBWL, 0);
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out_be32(&rcpm->ctbenrl, mask);
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#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
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/*
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* Disabling Boot Page Translation allows the memory region 0xfffff000
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* to 0xffffffff to be used normally. Leaving Boot Page Translation
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* enabled remaps 0xfffff000 to SDRAM which makes that memory region
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* unusable for normal operation but it does allow OSes to easily
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* reset a processor core to put it back into U-Boot's spinloop.
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*/
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clrbits_be32(&ccm->bstrar, LAW_EN);
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#endif
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}
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#else
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static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
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{
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u32 up, cpu_up_mask, whoami;
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u32 *table = (u32 *)&__spin_table;
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volatile u32 bpcr;
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volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
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u32 devdisr;
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int timeout = 10;
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whoami = in_be32(&pic->whoami);
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out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
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/* disable time base at the platform */
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devdisr = in_be32(&gur->devdisr);
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if (whoami)
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devdisr |= MPC85xx_DEVDISR_TB0;
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else
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devdisr |= MPC85xx_DEVDISR_TB1;
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out_be32(&gur->devdisr, devdisr);
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/* release the hounds */
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up = ((1 << cpu_numcores()) - 1);
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bpcr = in_be32(&ecm->eebpcr);
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bpcr |= (up << 24);
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out_be32(&ecm->eebpcr, bpcr);
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asm("sync; isync; msync");
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cpu_up_mask = 1 << whoami;
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/* wait for everyone */
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while (timeout) {
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int i;
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for (i = 0; i < cpu_numcores(); i++) {
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if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
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cpu_up_mask |= (1 << i);
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};
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if ((cpu_up_mask & up) == up)
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break;
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udelay(100);
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timeout--;
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}
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if (timeout == 0)
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printf("CPU up timeout. CPU up mask is %x should be %x\n",
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cpu_up_mask, up);
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/* enable time base at the platform */
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if (whoami)
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devdisr |= MPC85xx_DEVDISR_TB1;
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else
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devdisr |= MPC85xx_DEVDISR_TB0;
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out_be32(&gur->devdisr, devdisr);
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/* readback to sync write */
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in_be32(&gur->devdisr);
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mtspr(SPRN_TBWU, 0);
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mtspr(SPRN_TBWL, 0);
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devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
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out_be32(&gur->devdisr, devdisr);
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#ifdef CONFIG_MPC8xxx_DISABLE_BPTR
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/*
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* Disabling Boot Page Translation allows the memory region 0xfffff000
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* to 0xffffffff to be used normally. Leaving Boot Page Translation
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* enabled remaps 0xfffff000 to SDRAM which makes that memory region
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* unusable for normal operation but it does allow OSes to easily
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* reset a processor core to put it back into U-Boot's spinloop.
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*/
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clrbits_be32(&ecm->bptr, 0x80000000);
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#endif
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}
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#endif
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void cpu_mp_lmb_reserve(struct lmb *lmb)
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{
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u32 bootpg = determine_mp_bootpg(NULL);
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lmb_reserve(lmb, bootpg, 4096);
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}
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void setup_mp(void)
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{
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extern u32 __secondary_start_page;
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extern u32 __bootpg_addr, __spin_table_addr, __second_half_boot_page;
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int i;
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ulong fixup = (u32)&__secondary_start_page;
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u32 bootpg, bootpg_map, pagesize;
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bootpg = determine_mp_bootpg(&pagesize);
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/*
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* pagesize is only 4K or 8K
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* we only use the last 4K of boot page
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* bootpg_map saves the address for the boot page
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* 8K is used for the workaround of 3-way DDR interleaving
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*/
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bootpg_map = bootpg;
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if (pagesize == 8192)
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bootpg += 4096; /* use 2nd half */
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/* Some OSes expect secondary cores to be held in reset */
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if (hold_cores_in_reset(0))
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return;
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/*
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* Store the bootpg's cache-able half address for use by secondary
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* CPU cores to continue to boot
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*/
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__bootpg_addr = (u32)virt_to_phys(&__second_half_boot_page);
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/* Store spin table's physical address for use by secondary cores */
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__spin_table_addr = (u32)get_spin_phys_addr();
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/* flush bootpg it before copying invalidate any staled cacheline */
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flush_cache(bootpg, 4096);
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/* look for the tlb covering the reset page, there better be one */
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i = find_tlb_idx((void *)CONFIG_BPTR_VIRT_ADDR, 1);
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/* we found a match */
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if (i != -1) {
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/* map reset page to bootpg so we can copy code there */
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disable_tlb(i);
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set_tlb(1, CONFIG_BPTR_VIRT_ADDR, bootpg, /* tlb, epn, rpn */
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
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0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
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memcpy((void *)CONFIG_BPTR_VIRT_ADDR, (void *)fixup, 4096);
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plat_mp_up(bootpg_map, pagesize);
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} else {
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puts("WARNING: No reset page TLB. "
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"Skipping secondary core setup\n");
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}
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}
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