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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
183 lines
5.1 KiB
C
183 lines
5.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2009-2012 Freescale Semiconductor, Inc
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/fsl_law.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_A003399_NOR_WORKAROUND
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void setup_ifc(void)
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{
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struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
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u32 _mas0, _mas1, _mas2, _mas3, _mas7;
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phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
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/*
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* Adjust the TLB we were running out of to match the phys addr of the
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* chip select we are adjusting and will return to.
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*/
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flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
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_mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
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_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
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MAS1_TSIZE(BOOKE_PAGESZ_4M);
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_mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
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_mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
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_mas7 = FSL_BOOKE_MAS7(flash_phys);
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mtspr(MAS0, _mas0);
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mtspr(MAS1, _mas1);
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mtspr(MAS2, _mas2);
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mtspr(MAS3, _mas3);
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mtspr(MAS7, _mas7);
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asm volatile("isync;msync;tlbwe;isync");
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#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
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/*
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* TLB entry for debuggging in AS1
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* Create temporary TLB entry in AS0 to handle debug exception
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* As on debug exception MSR is cleared i.e. Address space is changed
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* to 0. A TLB entry (in AS0) is required to handle debug exception generated
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* in AS1.
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*
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* TLB entry is created for IVPR + IVOR15 to map on valid OP code address
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* bacause flash's physical address is going to change as
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* CONFIG_SYS_FLASH_BASE_PHYS.
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*/
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_mas0 = MAS0_TLBSEL(1) |
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MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
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_mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
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MAS1_TSIZE(BOOKE_PAGESZ_4M);
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_mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
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_mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
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_mas7 = FSL_BOOKE_MAS7(flash_phys);
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mtspr(MAS0, _mas0);
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mtspr(MAS1, _mas1);
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mtspr(MAS2, _mas2);
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mtspr(MAS3, _mas3);
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mtspr(MAS7, _mas7);
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asm volatile("isync;msync;tlbwe;isync");
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#endif
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/* Change flash's physical address */
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ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
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ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
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ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
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return ;
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}
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#endif
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/* We run cpu_init_early_f in AS = 1 */
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void cpu_init_early_f(void *fdt)
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{
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u32 mas0, mas1, mas2, mas3, mas7;
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#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#endif
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#ifdef CONFIG_A003399_NOR_WORKAROUND
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ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
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u32 *dst, *src;
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void (*setup_ifc_sram)(void);
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int i;
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#endif
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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/* gd area was zeroed during startup */
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#ifdef CONFIG_ARCH_QEMU_E500
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/*
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* CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
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* so we need to populate it before it accesses it.
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*/
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gd->fdt_blob = fdt;
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#endif
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mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
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mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
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mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
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mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
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mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
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write_tlb(mas0, mas1, mas2, mas3, mas7);
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/*
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* Work Around for IFC Erratum A-003549. This issue is P1010
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* specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
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* Hence specifically selecting CS3.
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*/
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#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
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setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
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#endif
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init_laws();
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/*
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* Work Around for IFC Erratum A003399, issue will hit only when execution
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* from NOR Flash
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*/
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#ifdef CONFIG_A003399_NOR_WORKAROUND
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#define SRAM_BASE_ADDR (0x00000000)
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/* TLB for SRAM */
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mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
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mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
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MAS1_TSIZE(BOOKE_PAGESZ_1M);
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mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
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mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
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mas7 = FSL_BOOKE_MAS7(0);
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write_tlb(mas0, mas1, mas2, mas3, mas7);
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out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
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out_be32(&l2cache->l2errdis,
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(MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
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out_be32(&l2cache->l2ctl,
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(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
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/*
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* Copy the code in setup_ifc to L2SRAM. Do a word copy
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* because NOR Flash on P1010 does not support byte
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* access (Erratum IFC-A002769)
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*/
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setup_ifc_sram = (void *)SRAM_BASE_ADDR;
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dst = (u32 *) SRAM_BASE_ADDR;
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src = (u32 *) setup_ifc;
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for (i = 0; i < 1024; i++) {
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/* cppcheck-suppress nullPointer */
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*dst++ = *src++;
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}
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/* cppcheck-suppress nullPointer */
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setup_ifc_sram();
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/* CLEANUP */
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clrbits_be32(&l2cache->l2ctl,
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(MPC85xx_L2CTL_L2E |
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MPC85xx_L2CTL_L2SRAM_ENTIRE));
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out_be32(&l2cache->l2srbar0, 0x0);
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#endif
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invalidate_tlb(1);
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#if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \
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!(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
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!defined(CONFIG_NAND_SPL)
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disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
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#endif
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init_tlbs();
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}
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