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![Simon Glass](/assets/img/avatar_default.png)
Move these fields into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org>
187 lines
4.8 KiB
C
187 lines
4.8 KiB
C
/*
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* Adapted for Motorola MPC8560 chips
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* Xianghua Xiao <x.xiao@motorola.com>
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*
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* This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's
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* copyright notice:
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*
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* General Purpose functions for the global management of the
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* 8220 Communication Processor Module.
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* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
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* Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
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* 2.3.99 Updates
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* Copyright (c) 2003 Motorola,Inc.
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*
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* In addition to the individual control of the communication
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* channels, there are a few functions that globally affect the
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* communication processor.
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*
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* Buffer descriptors must be allocated from the dual ported memory
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* space. The allocator for that is here. When the communication
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* process is reset, we reclaim the memory available. There is
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* currently no deallocator for this memory.
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*/
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#include <common.h>
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#include <asm/cpm_85xx.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* because we have stack and init data in dual port ram
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* we must reduce the size
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*/
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#undef CPM_DATAONLY_SIZE
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#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
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void
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m8560_cpm_reset(void)
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{
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volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
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volatile ulong count;
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gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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/* Reclaim the DP memory for our use.
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*/
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gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
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gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;
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/*
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* Reset CPM
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*/
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cpm->im_cpm_cp.cpcr = CPM_CR_RST;
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count = 0;
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do { /* Spin until command processed */
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__asm__ __volatile__ ("eieio");
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} while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
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}
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/* Allocate some memory from the dual ported ram.
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* To help protocols with object alignment restrictions, we do that
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* if they ask.
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*/
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uint
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m8560_cpm_dpalloc(uint size, uint align)
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{
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volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
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uint retloc;
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uint align_mask, off;
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uint savebase;
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align_mask = align - 1;
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savebase = gd->arch.dp_alloc_base;
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off = gd->arch.dp_alloc_base & align_mask;
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if (off != 0)
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gd->arch.dp_alloc_base += (align - off);
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if ((off = size & align_mask) != 0)
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size += align - off;
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if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
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gd->arch.dp_alloc_base = savebase;
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panic("m8560_cpm_dpalloc: ran out of dual port ram!");
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}
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retloc = gd->arch.dp_alloc_base;
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gd->arch.dp_alloc_base += size;
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memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
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return(retloc);
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}
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/* We also own one page of host buffer space for the allocation of
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* UART "fifos" and the like.
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*/
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uint
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m8560_cpm_hostalloc(uint size, uint align)
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{
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/* the host might not even have RAM yet - just use dual port RAM */
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return (m8560_cpm_dpalloc(size, align));
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}
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/* Set a baud rate generator. This needs lots of work. There are
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* eight BRGs, which can be connected to the CPM channels or output
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* as clocks. The BRGs are in two different block of internal
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* memory mapped space.
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* The baud rate clock is the system clock divided by something.
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* It was set up long ago during the initial boot phase and is
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* is given to us.
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* Baud rate clocks are zero-based in the driver code (as that maps
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* to port numbers). Documentation uses 1-based numbering.
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*/
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#define BRG_INT_CLK gd->arch.brg_clk
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#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
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/* This function is used by UARTS, or anything else that uses a 16x
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* oversampled clock.
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*/
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void
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m8560_cpm_setbrg(uint brg, uint rate)
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{
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volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
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volatile uint *bp;
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/* This is good enough to get SMCs running.....
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*/
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if (brg < 4) {
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bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
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}
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else {
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bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
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brg -= 4;
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}
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bp += brg;
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*bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
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}
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/* This function is used to set high speed synchronous baud rate
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* clocks.
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*/
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void
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m8560_cpm_fastbrg(uint brg, uint rate, int div16)
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{
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volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
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volatile uint *bp;
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/* This is good enough to get SMCs running.....
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*/
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if (brg < 4) {
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bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
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}
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else {
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bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
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brg -= 4;
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}
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bp += brg;
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*bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
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if (div16)
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*bp |= CPM_BRG_DIV16;
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}
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/* This function is used to set baud rate generators using an external
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* clock source and 16x oversampling.
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*/
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void
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m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
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{
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volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
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volatile uint *bp;
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if (brg < 4) {
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bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
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}
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else {
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bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
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brg -= 4;
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}
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bp += brg;
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*bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
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if (pinsel == 0)
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*bp |= CPM_BRG_EXTC_CLK3_9;
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else
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*bp |= CPM_BRG_EXTC_CLK5_15;
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}
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