mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 09:58:52 +09:00
![Joe Hershberger](/assets/img/avatar_default.png)
Update the naming convention used in the network stack functions and variables that Ethernet drivers use to interact with it. This cleans up the temporary hacks that were added to this interface along with the DM support. This patch has a few remaining checkpatch.pl failures that would be out of the scope of this patch to fix (drivers that are in gross violation of checkpatch.pl). Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
499 lines
12 KiB
C
499 lines
12 KiB
C
/*
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* Driver for Blackfin On-Chip MAC device
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*
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* Copyright (c) 2005-2008 Analog Device, Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <config.h>
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#include <net.h>
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#include <netdev.h>
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#include <command.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <linux/mii.h>
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#include <asm/blackfin.h>
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#include <asm/clock.h>
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#include <asm/portmux.h>
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#include <asm/mach-common/bits/dma.h>
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#include <asm/mach-common/bits/emac.h>
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#include <asm/mach-common/bits/pll.h>
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#include "bfin_mac.h"
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#ifndef CONFIG_PHY_ADDR
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# define CONFIG_PHY_ADDR 1
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#endif
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#ifndef CONFIG_PHY_CLOCK_FREQ
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# define CONFIG_PHY_CLOCK_FREQ 2500000
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#endif
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#ifdef CONFIG_POST
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#include <post.h>
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#endif
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#define RXBUF_BASE_ADDR 0xFF900000
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#define TXBUF_BASE_ADDR 0xFF800000
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#define TX_BUF_CNT 1
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#define TOUT_LOOP 1000000
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static ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
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static ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];
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static u16 txIdx; /* index of the current RX buffer */
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static u16 rxIdx; /* index of the current TX buffer */
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/* DMAx_CONFIG values at DMA Restart */
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static const union {
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u16 data;
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ADI_DMA_CONFIG_REG reg;
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} txdmacfg = {
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.reg = {
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.b_DMA_EN = 1, /* enabled */
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.b_WNR = 0, /* read from memory */
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.b_WDSIZE = 2, /* wordsize is 32 bits */
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.b_DMA2D = 0,
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.b_RESTART = 0,
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.b_DI_SEL = 0,
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.b_DI_EN = 0, /* no interrupt */
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.b_NDSIZE = 5, /* 5 half words is desc size */
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.b_FLOW = 7 /* large desc flow */
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},
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};
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static int bfin_miiphy_wait(void)
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{
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/* poll the STABUSY bit */
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while (bfin_read_EMAC_STAADD() & STABUSY)
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continue;
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return 0;
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}
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static int bfin_miiphy_read(const char *devname, uchar addr, uchar reg, ushort *val)
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{
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if (bfin_miiphy_wait())
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return 1;
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bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY);
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if (bfin_miiphy_wait())
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return 1;
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*val = bfin_read_EMAC_STADAT();
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return 0;
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}
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static int bfin_miiphy_write(const char *devname, uchar addr, uchar reg, ushort val)
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{
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if (bfin_miiphy_wait())
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return 1;
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bfin_write_EMAC_STADAT(val);
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bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STAOP | STABUSY);
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return 0;
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}
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int bfin_EMAC_initialize(bd_t *bis)
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{
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struct eth_device *dev;
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dev = malloc(sizeof(*dev));
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if (dev == NULL)
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hang();
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memset(dev, 0, sizeof(*dev));
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strcpy(dev->name, "bfin_mac");
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dev->iobase = 0;
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dev->priv = 0;
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dev->init = bfin_EMAC_init;
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dev->halt = bfin_EMAC_halt;
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dev->send = bfin_EMAC_send;
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dev->recv = bfin_EMAC_recv;
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dev->write_hwaddr = bfin_EMAC_setup_addr;
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eth_register(dev);
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#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
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miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write);
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#endif
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return 0;
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}
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static int bfin_EMAC_send(struct eth_device *dev, void *packet, int length)
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{
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int i;
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int result = 0;
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if (length <= 0) {
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printf("Ethernet: bad packet size: %d\n", length);
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goto out;
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}
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if (bfin_read_DMA2_IRQ_STATUS() & DMA_ERR) {
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printf("Ethernet: tx DMA error\n");
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goto out;
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}
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for (i = 0; (bfin_read_DMA2_IRQ_STATUS() & DMA_RUN); ++i) {
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if (i > TOUT_LOOP) {
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puts("Ethernet: tx time out\n");
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goto out;
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}
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}
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txbuf[txIdx]->FrmData->NoBytes = length;
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memcpy(txbuf[txIdx]->FrmData->Dest, (void *)packet, length);
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txbuf[txIdx]->Dma[0].START_ADDR = (u32) txbuf[txIdx]->FrmData;
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bfin_write_DMA2_NEXT_DESC_PTR(txbuf[txIdx]->Dma);
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bfin_write_DMA2_CONFIG(txdmacfg.data);
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bfin_write_EMAC_OPMODE(bfin_read_EMAC_OPMODE() | TE);
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for (i = 0; (txbuf[txIdx]->StatusWord & TX_COMP) == 0; i++) {
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if (i > TOUT_LOOP) {
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puts("Ethernet: tx error\n");
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goto out;
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}
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}
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result = txbuf[txIdx]->StatusWord;
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txbuf[txIdx]->StatusWord = 0;
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if ((txIdx + 1) >= TX_BUF_CNT)
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txIdx = 0;
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else
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txIdx++;
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out:
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debug("BFIN EMAC send: length = %d\n", length);
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return result;
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}
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static int bfin_EMAC_recv(struct eth_device *dev)
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{
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int length = 0;
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for (;;) {
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if ((rxbuf[rxIdx]->StatusWord & RX_COMP) == 0) {
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length = -1;
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break;
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}
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if ((rxbuf[rxIdx]->StatusWord & RX_DMAO) != 0) {
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printf("Ethernet: rx dma overrun\n");
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break;
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}
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if ((rxbuf[rxIdx]->StatusWord & RX_OK) == 0) {
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printf("Ethernet: rx error\n");
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break;
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}
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length = rxbuf[rxIdx]->StatusWord & 0x000007FF;
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if (length <= 4) {
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printf("Ethernet: bad frame\n");
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break;
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}
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debug("%s: len = %d\n", __func__, length - 4);
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net_rx_packets[rxIdx] = rxbuf[rxIdx]->FrmData->Dest;
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net_process_received_packet(net_rx_packets[rxIdx], length - 4);
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bfin_write_DMA1_IRQ_STATUS(DMA_DONE | DMA_ERR);
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rxbuf[rxIdx]->StatusWord = 0x00000000;
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if ((rxIdx + 1) >= PKTBUFSRX)
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rxIdx = 0;
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else
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rxIdx++;
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}
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return length;
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}
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/**************************************************************
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*
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* Ethernet Initialization Routine
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*
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*************************************************************/
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/* MDC = SCLK / MDC_freq / 2 - 1 */
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#define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
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#ifndef CONFIG_BFIN_MAC_PINS
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# ifdef CONFIG_RMII
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# define CONFIG_BFIN_MAC_PINS P_RMII0
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# else
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# define CONFIG_BFIN_MAC_PINS P_MII0
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# endif
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#endif
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static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
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{
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const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
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u16 phydat;
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size_t count;
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/* Enable PHY output */
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bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE);
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/* Set all the pins to peripheral mode */
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peripheral_request_list(pins, "bfin_mac");
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/* Odd word alignment for Receive Frame DMA word */
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/* Configure checksum support and rcve frame word alignment */
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bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ)));
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/* turn on auto-negotiation and wait for link to come up */
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bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE);
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count = 0;
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while (1) {
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++count;
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if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat))
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return -1;
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if (phydat & BMSR_LSTATUS)
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break;
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if (count > 30000) {
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printf("%s: link down, check cable\n", dev->name);
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return -1;
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}
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udelay(100);
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}
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/* see what kind of link we have */
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if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat))
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return -1;
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if (phydat & LPA_DUPLEX)
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*opmode = FDMODE;
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else
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*opmode = 0;
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bfin_write_EMAC_MMC_CTL(RSTC | CROLL);
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bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL);
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bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL);
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/* Initialize the TX DMA channel registers */
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bfin_write_DMA2_X_COUNT(0);
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bfin_write_DMA2_X_MODIFY(4);
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bfin_write_DMA2_Y_COUNT(0);
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bfin_write_DMA2_Y_MODIFY(0);
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/* Initialize the RX DMA channel registers */
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bfin_write_DMA1_X_COUNT(0);
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bfin_write_DMA1_X_MODIFY(4);
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bfin_write_DMA1_Y_COUNT(0);
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bfin_write_DMA1_Y_MODIFY(0);
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return 0;
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}
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static int bfin_EMAC_setup_addr(struct eth_device *dev)
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{
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bfin_write_EMAC_ADDRLO(
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dev->enetaddr[0] |
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dev->enetaddr[1] << 8 |
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dev->enetaddr[2] << 16 |
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dev->enetaddr[3] << 24
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);
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bfin_write_EMAC_ADDRHI(
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dev->enetaddr[4] |
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dev->enetaddr[5] << 8
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);
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return 0;
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}
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static int bfin_EMAC_init(struct eth_device *dev, bd_t *bd)
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{
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u32 opmode;
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int dat;
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int i;
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debug("Eth_init: ......\n");
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txIdx = 0;
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rxIdx = 0;
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/* Initialize System Register */
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if (bfin_miiphy_init(dev, &dat) < 0)
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return -1;
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/* Initialize EMAC address */
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bfin_EMAC_setup_addr(dev);
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/* Initialize TX and RX buffer */
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for (i = 0; i < PKTBUFSRX; i++) {
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rxbuf[i] = SetupRxBuffer(i);
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if (i > 0) {
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rxbuf[i - 1]->Dma[1].NEXT_DESC_PTR = rxbuf[i]->Dma;
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if (i == (PKTBUFSRX - 1))
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rxbuf[i]->Dma[1].NEXT_DESC_PTR = rxbuf[0]->Dma;
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}
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}
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for (i = 0; i < TX_BUF_CNT; i++) {
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txbuf[i] = SetupTxBuffer(i);
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if (i > 0) {
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txbuf[i - 1]->Dma[1].NEXT_DESC_PTR = txbuf[i]->Dma;
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if (i == (TX_BUF_CNT - 1))
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txbuf[i]->Dma[1].NEXT_DESC_PTR = txbuf[0]->Dma;
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}
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}
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/* Set RX DMA */
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bfin_write_DMA1_NEXT_DESC_PTR(rxbuf[0]->Dma);
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bfin_write_DMA1_CONFIG(rxbuf[0]->Dma[0].CONFIG_DATA);
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/* Wait MII done */
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bfin_miiphy_wait();
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/* We enable only RX here */
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/* ASTP : Enable Automatic Pad Stripping
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PR : Promiscuous Mode for test
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PSF : Receive frames with total length less than 64 bytes.
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FDMODE : Full Duplex Mode
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LB : Internal Loopback for test
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RE : Receiver Enable */
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if (dat == FDMODE)
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opmode = ASTP | FDMODE | PSF;
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else
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opmode = ASTP | PSF;
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opmode |= RE;
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#ifdef CONFIG_RMII
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opmode |= TE | RMII;
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#endif
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/* Turn on the EMAC */
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bfin_write_EMAC_OPMODE(opmode);
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return 0;
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}
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static void bfin_EMAC_halt(struct eth_device *dev)
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{
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debug("Eth_halt: ......\n");
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/* Turn off the EMAC */
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bfin_write_EMAC_OPMODE(0);
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/* Turn off the EMAC RX DMA */
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bfin_write_DMA1_CONFIG(0);
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bfin_write_DMA2_CONFIG(0);
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}
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ADI_ETHER_BUFFER *SetupRxBuffer(int no)
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{
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ADI_ETHER_FRAME_BUFFER *frmbuf;
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ADI_ETHER_BUFFER *buf;
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int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
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int total_size = nobytes_buffer + RECV_BUFSIZE;
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buf = (void *) (RXBUF_BASE_ADDR + no * total_size);
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frmbuf = (void *) (RXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
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memset(buf, 0x00, nobytes_buffer);
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buf->FrmData = frmbuf;
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memset(frmbuf, 0xfe, RECV_BUFSIZE);
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/* set up first desc to point to receive frame buffer */
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buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
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buf->Dma[0].START_ADDR = (u32) buf->FrmData;
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buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
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buf->Dma[0].CONFIG.b_WNR = 1; /* Write to memory */
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buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
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buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
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buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
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/* set up second desc to point to status word */
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buf->Dma[1].NEXT_DESC_PTR = buf->Dma;
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buf->Dma[1].START_ADDR = (u32) & buf->IPHdrChksum;
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buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
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buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
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buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
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buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
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buf->Dma[1].CONFIG.b_NDSIZE = 5; /* must be 0 when FLOW is 0 */
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buf->Dma[1].CONFIG.b_FLOW = 7; /* stop */
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return buf;
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}
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ADI_ETHER_BUFFER *SetupTxBuffer(int no)
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{
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ADI_ETHER_FRAME_BUFFER *frmbuf;
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ADI_ETHER_BUFFER *buf;
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int nobytes_buffer = sizeof(ADI_ETHER_BUFFER[2]) / 2; /* ensure a multi. of 4 */
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int total_size = nobytes_buffer + RECV_BUFSIZE;
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buf = (void *) (TXBUF_BASE_ADDR + no * total_size);
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frmbuf = (void *) (TXBUF_BASE_ADDR + no * total_size + nobytes_buffer);
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memset(buf, 0x00, nobytes_buffer);
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buf->FrmData = frmbuf;
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memset(frmbuf, 0x00, RECV_BUFSIZE);
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/* set up first desc to point to receive frame buffer */
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buf->Dma[0].NEXT_DESC_PTR = &(buf->Dma[1]);
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buf->Dma[0].START_ADDR = (u32) buf->FrmData;
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buf->Dma[0].CONFIG.b_DMA_EN = 1; /* enabled */
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buf->Dma[0].CONFIG.b_WNR = 0; /* Read to memory */
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buf->Dma[0].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
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buf->Dma[0].CONFIG.b_NDSIZE = 5; /* 5 half words is desc size. */
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buf->Dma[0].CONFIG.b_FLOW = 7; /* large desc flow */
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/* set up second desc to point to status word */
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buf->Dma[1].NEXT_DESC_PTR = &(buf->Dma[0]);
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buf->Dma[1].START_ADDR = (u32) & buf->StatusWord;
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buf->Dma[1].CONFIG.b_DMA_EN = 1; /* enabled */
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buf->Dma[1].CONFIG.b_WNR = 1; /* Write to memory */
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buf->Dma[1].CONFIG.b_WDSIZE = 2; /* wordsize is 32 bits */
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buf->Dma[1].CONFIG.b_DI_EN = 1; /* enable interrupt */
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buf->Dma[1].CONFIG.b_NDSIZE = 0; /* must be 0 when FLOW is 0 */
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buf->Dma[1].CONFIG.b_FLOW = 0; /* stop */
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return buf;
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}
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#if defined(CONFIG_POST) && defined(CONFIG_SYS_POST_ETHER)
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int ether_post_test(int flags)
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{
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uchar buf[64];
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int i, value = 0;
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int length;
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uint addr;
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printf("\n--------");
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bfin_EMAC_init(NULL, NULL);
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/* construct the package */
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addr = bfin_read_EMAC_ADDRLO();
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buf[0] = buf[6] = addr;
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buf[1] = buf[7] = addr >> 8;
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buf[2] = buf[8] = addr >> 16;
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buf[3] = buf[9] = addr >> 24;
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addr = bfin_read_EMAC_ADDRHI();
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buf[4] = buf[10] = addr;
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buf[5] = buf[11] = addr >> 8;
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buf[12] = 0x08; /* Type: ARP */
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buf[13] = 0x06;
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buf[14] = 0x00; /* Hardware type: Ethernet */
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buf[15] = 0x01;
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buf[16] = 0x08; /* Protocal type: IP */
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buf[17] = 0x00;
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buf[18] = 0x06; /* Hardware size */
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buf[19] = 0x04; /* Protocol size */
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buf[20] = 0x00; /* Opcode: request */
|
|
buf[21] = 0x01;
|
|
|
|
for (i = 0; i < 42; i++)
|
|
buf[i + 22] = i;
|
|
printf("--------Send 64 bytes......\n");
|
|
bfin_EMAC_send(NULL, buf, 64);
|
|
for (i = 0; i < 100; i++) {
|
|
udelay(10000);
|
|
if ((rxbuf[rxIdx]->StatusWord & RX_COMP) != 0) {
|
|
value = 1;
|
|
break;
|
|
}
|
|
}
|
|
if (value == 0) {
|
|
printf("--------EMAC can't receive any data\n");
|
|
eth_halt();
|
|
return -1;
|
|
}
|
|
length = rxbuf[rxIdx]->StatusWord & 0x000007FF - 4;
|
|
for (i = 0; i < length; i++) {
|
|
if (rxbuf[rxIdx]->FrmData->Dest[i] != buf[i]) {
|
|
printf("--------EMAC receive error data!\n");
|
|
eth_halt();
|
|
return -1;
|
|
}
|
|
}
|
|
printf("--------receive %d bytes, matched\n", length);
|
|
bfin_EMAC_halt(NULL);
|
|
return 0;
|
|
}
|
|
#endif
|