mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
141 lines
3.6 KiB
C
141 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2013 Broadcom Corporation.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sysmap.h>
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#define GPIO_BASE (void *)GPIO2_BASE_ADDR
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#define GPIO_PASSWD 0x00a5a501
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#define GPIO_PER_BANK 32
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#define GPIO_MAX_BANK_NUM 8
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#define GPIO_BANK(gpio) ((gpio) >> 5)
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#define GPIO_BITMASK(gpio) \
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(1UL << ((gpio) & (GPIO_PER_BANK - 1)))
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#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
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#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
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#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
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#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
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#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
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#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
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#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
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#define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2))
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#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
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#define GPIO_GPPWR_OFFSET 0x00000520
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#define GPIO_GPCTR0_DBR_SHIFT 5
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#define GPIO_GPCTR0_DBR_MASK 0x000001e0
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#define GPIO_GPCTR0_ITR_SHIFT 3
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#define GPIO_GPCTR0_ITR_MASK 0x00000018
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#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
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#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
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#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
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#define GPIO_GPCTR0_IOTR_MASK 0x00000001
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#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
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#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
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int gpio_request(unsigned gpio, const char *label)
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{
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unsigned int value, off;
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writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET);
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off = GPIO_PWD_STATUS(GPIO_BANK(gpio));
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value = readl(GPIO_BASE + off) & ~GPIO_BITMASK(gpio);
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writel(value, GPIO_BASE + off);
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return 0;
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}
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int gpio_free(unsigned gpio)
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{
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unsigned int value, off;
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writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET);
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off = GPIO_PWD_STATUS(GPIO_BANK(gpio));
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value = readl(GPIO_BASE + off) | GPIO_BITMASK(gpio);
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writel(value, GPIO_BASE + off);
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return 0;
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}
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int gpio_direction_input(unsigned gpio)
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{
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u32 val;
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val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_IOTR_MASK;
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val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
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writel(val, GPIO_BASE + GPIO_CONTROL(gpio));
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return 0;
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}
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int gpio_direction_output(unsigned gpio, int value)
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{
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int bank_id = GPIO_BANK(gpio);
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int bitmask = GPIO_BITMASK(gpio);
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u32 val, off;
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val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_IOTR_MASK;
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val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
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writel(val, GPIO_BASE + GPIO_CONTROL(gpio));
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off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
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val = readl(GPIO_BASE + off);
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val |= bitmask;
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writel(val, GPIO_BASE + off);
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return 0;
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}
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int gpio_get_value(unsigned gpio)
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{
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int bank_id = GPIO_BANK(gpio);
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int bitmask = GPIO_BITMASK(gpio);
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u32 val, off;
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/* determine the GPIO pin direction */
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val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
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val &= GPIO_GPCTR0_IOTR_MASK;
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/* read the GPIO bank status */
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off = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ?
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GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id);
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val = readl(GPIO_BASE + off);
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/* return the specified bit status */
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return !!(val & bitmask);
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}
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void gpio_set_value(unsigned gpio, int value)
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{
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int bank_id = GPIO_BANK(gpio);
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int bitmask = GPIO_BITMASK(gpio);
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u32 val, off;
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/* determine the GPIO pin direction */
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val = readl(GPIO_BASE + GPIO_CONTROL(gpio));
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val &= GPIO_GPCTR0_IOTR_MASK;
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/* this function only applies to output pin */
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if (GPIO_GPCTR0_IOTR_CMD_INPUT == val) {
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printf("%s: Cannot set an input pin %d\n", __func__, gpio);
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return;
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}
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off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
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val = readl(GPIO_BASE + off);
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val |= bitmask;
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writel(val, GPIO_BASE + off);
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}
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