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https://github.com/brain-hackers/u-boot-brain
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4f1d1b7d1e
P2041RDB Specification: ----------------------- Memory subsystem: * 4Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus) * 128 Mbyte NOR flash single-chip memory * 256 Kbit M24256 I2C EEPROM * 16 Mbyte SPI memory * SD connector to interface with the SD memory card Ethernet: * dTSEC1: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC2: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC3: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC4: connected to the Vitesse RGMII PHY (VSC8641) * dTSEC5: connected to the Vitesse RGMII PHY (VSC8641) PCIe: * Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1 * Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2 SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces I2C: * I2C1: Real time clock, Temperature sensor, Memory module * I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2 UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
54 lines
2.0 KiB
C
54 lines
2.0 KiB
C
/**
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* Copyright 2011 Freescale Semiconductor
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* Author: Mingkai Hu <Mingkai.hu@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This file provides support for the ngPIXIS, a board-specific FPGA used on
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* some Freescale reference boards.
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*/
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/*
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* CPLD register set. Feel free to add board-specific #ifdefs where necessary.
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*/
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typedef struct cpld_data {
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u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */
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u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */
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u8 pcba_ver; /* 0x2 - PCBA Revision Register */
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u8 system_rst; /* 0x3 - system reset register */
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u8 wd_cfg; /* 0x4 - Watchdog Period Setting Register */
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u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */
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u8 por_cfg; /* 0x6 - POR Control Register */
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u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */
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u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */
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u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */
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u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */
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u8 fbank_sel; /* 0xb - Flash bank selection */
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u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */
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u8 sw[1]; /* 0xd - SW2 Status */
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} __attribute__ ((packed)) cpld_data_t;
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#define SERDES_MUX_LANE_6_MASK 0x2
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#define SERDES_MUX_LANE_6_SHIFT 1
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#define SERDES_MUX_LANE_A_MASK 0x1
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#define SERDES_MUX_LANE_A_SHIFT 0
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#define SERDES_MUX_LANE_C_MASK 0x4
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#define SERDES_MUX_LANE_C_SHIFT 2
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#define SERDES_MUX_LANE_D_MASK 0x8
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#define SERDES_MUX_LANE_D_SHIFT 3
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/* Pointer to the CPLD register set */
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#define cpld ((cpld_data_t *)CPLD_BASE)
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/* The CPLD SW register that corresponds to board switch X, where x >= 1 */
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#define CPLD_SW(x) (cpld->sw[(x) - 2])
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u8 cpld_read(unsigned int reg);
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void cpld_write(unsigned int reg, u8 value);
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#define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg))
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#define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value)
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