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https://github.com/brain-hackers/u-boot-brain
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f110fe940c
Configuring DCSRCR to define the DCSR space to be 1G instead of the default 4M. DCSRCR only allows selection of either 4M or 1G. Most DCSR registers are within 4M but the Nexus trace buffer is located at offset 16M within the DCSR. Configuring the LAW to be 32M to allow access to the Nexus trace buffer. No TLB modification is required since accessing the Nexus trace buffer from within u-boot is not required. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
49 lines
1.7 KiB
C
49 lines
1.7 KiB
C
/*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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#ifdef CONFIG_SYS_BMAN_MEM_PHYS
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SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
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#endif
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#ifdef CONFIG_SYS_QMAN_MEM_PHYS
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SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
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#endif
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SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
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#ifdef CONFIG_SYS_DCSRBAR_PHYS
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/* Limit DCSR to 32M to access NPC Trace Buffer */
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SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
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#endif
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#ifdef CONFIG_SYS_NAND_BASE_PHYS
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SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
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#endif
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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