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https://github.com/brain-hackers/u-boot-brain
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c916d7c914
The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
108 lines
2.9 KiB
C
108 lines
2.9 KiB
C
/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _ASM_CONFIG_H_
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#define _ASM_CONFIG_H_
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#ifdef CONFIG_MPC85xx
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#include <asm/config_mpc85xx.h>
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#endif
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#ifdef CONFIG_MPC86xx
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#include <asm/config_mpc86xx.h>
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#endif
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/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
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#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
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# ifndef CONFIG_HARD_SPI
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# define CONFIG_HARD_SPI
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# endif
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#endif
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#define CONFIG_LMB
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#define CONFIG_SYS_BOOT_RAMDISK_HIGH
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#define CONFIG_SYS_BOOT_GET_CMDLINE
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#define CONFIG_SYS_BOOT_GET_KBD
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#ifndef CONFIG_MAX_MEM_MAPPED
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#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
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#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
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#else
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#define CONFIG_MAX_MEM_MAPPED (256 << 20)
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#endif
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#endif
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/* Check if boards need to enable FSL DMA engine for SDRAM init */
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#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
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#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
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((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
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!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
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#define CONFIG_FSL_DMA
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#endif
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#endif
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#ifndef CONFIG_MAX_CPUS
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#define CONFIG_MAX_CPUS 1
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#endif
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/*
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* Provide a default boot page translation virtual address that lines up with
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* Freescale's default e500 reset page.
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*/
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#if (defined(CONFIG_E500) && defined(CONFIG_MP))
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#ifndef CONFIG_BPTR_VIRT_ADDR
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#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
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#endif
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#endif
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/*
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* SEC (crypto unit) major compatible version determination
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*/
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#if defined(CONFIG_MPC83xx)
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#endif
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/* Since so many PPC SOCs have a semi-common LBC, define this here */
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#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
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defined(CONFIG_MPC83xx)
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#if !defined(CONFIG_FSL_IFC)
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#define CONFIG_FSL_LBC
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#endif
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#endif
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/* The TSEC driver uses the PHYLIB infrastructure */
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#ifndef CONFIG_PHYLIB
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_PHYLIB
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#include <config_phylib_all_drivers.h>
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#endif /* TSEC_ENET */
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#endif /* !CONFIG_PHYLIB */
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/* The FMAN driver uses the PHYLIB infrastructure */
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#if defined(CONFIG_FMAN_ENET)
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#define CONFIG_PHYLIB
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#endif
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/* All PPC boards must swap IDE bytes */
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#define CONFIG_IDE_SWAP_IO
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#endif /* _ASM_CONFIG_H_ */
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