Anup Patel fdff1f96a6 riscv: Rename cpu/qemu to cpu/generic ... The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		2019-02-27 09:12:33 +08:00
..
ax25	riscv: move the AX25-specific implementation of flush_dcache_all	2019-01-15 09:36:31 +08:00
generic	riscv: Rename cpu/qemu to cpu/generic	2019-02-27 09:12:33 +08:00
cpu.c	riscv: Do some basic architecture level cpu initialization	2018-12-18 09:56:27 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Return to previous privilege level after trap handling	2018-12-18 09:56:27 +08:00
start.S	riscv: Save boot hart id to the global data	2018-12-18 09:56:27 +08:00
u-boot.lds	riscv: Make start.S available for all targets	2018-10-03 17:48:14 +08:00