mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
2a10f8b948
Add defines to use CONFIG_SYS_GENERIC_BOARD and CONFIG_OF_LIBFDT. Semi-separate to this: the size of the image for the da850evm has increased to the point that the size in da850evm.h and the offset for the environment in SPI flash no longer work. They are modified to account for the larger image size. Signed-off-by: Peter Howard <phoward@gme.net.au> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
407 lines
12 KiB
C
407 lines
12 KiB
C
/*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Based on davinci_dvevm.h. Original Copyrights follow:
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Board
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*/
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#define CONFIG_DRIVER_TI_EMAC
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/* check if direct NOR boot config is used */
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#ifndef CONFIG_DIRECT_NOR_BOOT
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#define CONFIG_USE_SPIFLASH
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#endif
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/*
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* SoC Configuration
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*/
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#define CONFIG_MACH_DAVINCI_DA850_EVM
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#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
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#define CONFIG_SOC_DA850 /* TI DA850 SoC */
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#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
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#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
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#define CONFIG_SYS_OSCIN_FREQ 24000000
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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#define CONFIG_SYS_DA850_PLL_INIT
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#define CONFIG_SYS_DA850_DDR_INIT
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#ifdef CONFIG_DIRECT_NOR_BOOT
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DA8XX_GPIO
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#define CONFIG_SYS_TEXT_BASE 0x60000000
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#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
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#define CONFIG_DA850_LOWLEVEL
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#else
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#define CONFIG_SYS_TEXT_BASE 0xc1080000
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#endif
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/*
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* Memory Info
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*/
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#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
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#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
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#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
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/* memtest start addr */
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
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/* memtest will be run on 16MB */
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#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
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DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
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DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
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DAVINCI_SYSCFG_SUSPSRC_UART2 | \
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DAVINCI_SYSCFG_SUSPSRC_EMAC | \
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DAVINCI_SYSCFG_SUSPSRC_I2C)
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/*
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* PLL configuration
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*/
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#define CONFIG_SYS_DV_CLKMODE 0
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#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
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#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
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#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
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#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
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#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
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#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
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#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
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#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
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#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
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#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLM 24
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#define CONFIG_SYS_DA850_PLL1_PLLM 21
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/*
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* DDR2 memory configuration
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*/
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#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
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DV_DDR_PHY_EXT_STRBEN | \
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(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
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(1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
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(1 << DV_DDR_SDCR_DDREN_SHIFT) | \
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(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
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(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
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(0x3 << DV_DDR_SDCR_CL_SHIFT) | \
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(0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
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(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
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/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
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#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
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#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
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(14 << DV_DDR_SDTMR1_RFC_SHIFT) | \
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(2 << DV_DDR_SDTMR1_RP_SHIFT) | \
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(2 << DV_DDR_SDTMR1_RCD_SHIFT) | \
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(1 << DV_DDR_SDTMR1_WR_SHIFT) | \
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(5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
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(8 << DV_DDR_SDTMR1_RC_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
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(0 << DV_DDR_SDTMR1_WTR_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
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(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
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(0 << DV_DDR_SDTMR2_XP_SHIFT) | \
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(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
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(17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
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(199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
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(0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
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(0 << DV_DDR_SDTMR2_CKE_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494
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#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
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/*
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* Serial Driver info
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*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
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#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
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#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
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#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
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#define CONFIG_BAUDRATE 115200 /* Default baud rate */
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#define CONFIG_SPI
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_SPI_FLASH_WINBOND
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#define CONFIG_CMD_SF
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#define CONFIG_DAVINCI_SPI
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#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
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#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
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#define CONFIG_SF_DEFAULT_SPEED 30000000
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#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
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#ifdef CONFIG_USE_SPIFLASH
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000
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#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
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#endif
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/*
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* I2C Configuration
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*/
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_DAVINCI
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#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
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#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
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#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
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/*
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* Flash & Environment
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*/
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#ifdef CONFIG_USE_NAND
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#undef CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_NAND_DAVINCI
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */
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#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */
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#define CONFIG_ENV_SIZE (128 << 10)
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
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#define CONFIG_SYS_NAND_PAGE_2K
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#define CONFIG_SYS_NAND_CS 3
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#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
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#define CONFIG_SYS_NAND_MASK_CLE 0x10
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#define CONFIG_SYS_NAND_MASK_ALE 0x8
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#undef CONFIG_SYS_NAND_HW_ECC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10)
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
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#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
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#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \
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CONFIG_SYS_NAND_U_BOOT_SIZE - \
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CONFIG_SYS_MALLOC_LEN - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_NAND_ECCPOS { \
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24, 25, 26, 27, 28, \
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29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
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39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
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49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
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59, 60, 61, 62, 63 }
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
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#define CONFIG_SYS_NAND_ECCSIZE 512
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#define CONFIG_SYS_NAND_ECCBYTES 10
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_ECC
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#define CONFIG_SPL_NAND_SIMPLE
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#define CONFIG_SPL_NAND_LOAD
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#endif
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/*
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* Network & Ethernet Configuration
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*/
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#ifdef CONFIG_DRIVER_TI_EMAC
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#define CONFIG_MII
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_NET_RETRY_COUNT 10
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#endif
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#ifdef CONFIG_USE_NOR
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_PROTECTION
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
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#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
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#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3)
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#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */
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#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
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#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */
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#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\
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+ 3)
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#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
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#endif
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#ifdef CONFIG_USE_SPIFLASH
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#undef CONFIG_ENV_IS_IN_FLASH
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#undef CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SIZE (64 << 10)
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#define CONFIG_ENV_OFFSET (512 << 10)
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#define CONFIG_ENV_SECT_SIZE (64 << 10)
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#define CONFIG_SYS_NO_FLASH
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#endif
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/*
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* U-Boot general configuration
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*/
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#define CONFIG_SYS_GENERIC_BOARD
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#define CONFIG_MISC_INIT_R
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOOTFILE "uImage" /* Boot file name */
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#define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
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#define CONFIG_VERSION_VARIABLE
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CRC32_VERIFY
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#define CONFIG_MX_CYCLIC
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#define CONFIG_OF_LIBFDT
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/*
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* Linux Information
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*/
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#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
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#define CONFIG_HWCONFIG /* enable hwconfig */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_BOOTARGS \
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"mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes"
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/*
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* U-Boot commands
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SAVES
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#define CONFIG_CMD_MEMORY
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#ifdef CONFIG_CMD_BDI
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#define CONFIG_CLOCKS
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#endif
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#ifndef CONFIG_DRIVER_TI_EMAC
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_DHCP
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#undef CONFIG_CMD_MII
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#undef CONFIG_CMD_PING
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#endif
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#ifdef CONFIG_USE_NAND
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_IMLS
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_LZO
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#define CONFIG_RBTREE
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#endif
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#ifdef CONFIG_USE_SPIFLASH
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_FLASH
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#define CONFIG_CMD_SPI
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#define CONFIG_CMD_SAVEENV
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#endif
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#if !defined(CONFIG_USE_NAND) && \
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!defined(CONFIG_USE_NOR) && \
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!defined(CONFIG_USE_SPIFLASH)
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#define CONFIG_ENV_IS_NOWHERE
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_ENV_SIZE (16 << 10)
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_ENV
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#endif
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/* SD/MMC configuration */
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#ifndef CONFIG_USE_NOR
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#define CONFIG_MMC
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#define CONFIG_DAVINCI_MMC_SD1
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DAVINCI_MMC
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#endif
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/*
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* Enable MMC commands only when
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* MMC support is present
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*/
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#ifdef CONFIG_MMC
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_MMC
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#endif
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#ifndef CONFIG_DIRECT_NOR_BOOT
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/* defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
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CONFIG_SYS_MALLOC_LEN)
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#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
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#define CONFIG_SPL_SPI_SUPPORT
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#define CONFIG_SPL_SPI_FLASH_SUPPORT
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#define CONFIG_SPL_SPI_LOAD
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
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#define CONFIG_SPL_STACK 0x8001ff00
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#define CONFIG_SPL_TEXT_BASE 0x80000000
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#define CONFIG_SPL_MAX_FOOTPRINT 32768
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#define CONFIG_SPL_PAD_TO 32768
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#endif
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/* Load U-Boot Image From MMC */
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#ifdef CONFIG_SPL_MMC_LOAD
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75
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#undef CONFIG_SPL_SPI_SUPPORT
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#undef CONFIG_SPL_SPI_LOAD
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#endif
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/* additions for new relocation code, must added to all boards */
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#define CONFIG_SYS_SDRAM_BASE 0xc0000000
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#ifdef CONFIG_DIRECT_NOR_BOOT
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#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00
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#else
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
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GENERATED_GBL_DATA_SIZE)
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#endif /* CONFIG_DIRECT_NOR_BOOT */
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#endif /* __CONFIG_H */
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