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https://github.com/brain-hackers/u-boot-brain
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331 lines
9.9 KiB
C
331 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Eric Gao <eric.gao@rock-chips.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <display.h>
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#include <dm.h>
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#include <log.h>
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#include <panel.h>
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#include <regmap.h>
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#include "rk_mipi.h"
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <dm/uclass-internal.h>
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#include <linux/kernel.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/cru.h>
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#include <asm/arch-rockchip/grf_rk3399.h>
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#include <asm/arch-rockchip/rockchip_mipi_dsi.h>
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DECLARE_GLOBAL_DATA_PTR;
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int rk_mipi_read_timing(struct udevice *dev,
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struct display_timing *timing)
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{
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int ret;
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ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, timing);
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if (ret) {
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debug("%s: Failed to decode display timing (ret=%d)\n",
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__func__, ret);
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Register write function used only for mipi dsi controller.
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* Parameter:
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* @regs: mipi controller address
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* @reg: combination of regaddr(16bit)|bitswidth(8bit)|offset(8bit) you can
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* use define in rk_mipi.h directly for this parameter
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* @val: value that will be write to specified bits of register
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*/
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static void rk_mipi_dsi_write(uintptr_t regs, u32 reg, u32 val)
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{
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u32 dat;
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u32 mask;
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u32 offset = (reg >> OFFSET_SHIFT) & 0xff;
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u32 bits = (reg >> BITS_SHIFT) & 0xff;
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uintptr_t addr = (reg >> ADDR_SHIFT) + regs;
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/* Mask for specifiled bits,the corresponding bits will be clear */
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mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits)));
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/* Make sure val in the available range */
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val &= ~(0xffffffff << bits);
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/* Get register's original val */
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dat = readl(addr);
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/* Clear specified bits */
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dat &= mask;
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/* Fill specified bits */
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dat |= val << offset;
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writel(dat, addr);
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}
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int rk_mipi_dsi_enable(struct udevice *dev,
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const struct display_timing *timing)
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{
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ofnode node, timing_node;
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int val;
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struct rk_mipi_priv *priv = dev_get_priv(dev);
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uintptr_t regs = priv->regs;
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u32 txbyte_clk = priv->txbyte_clk;
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u32 txesc_clk = priv->txesc_clk;
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txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1);
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/* Set Display timing parameter */
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rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ);
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rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ);
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rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ
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+ timing->hback_porch.typ + timing->hactive.typ
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+ timing->hfront_porch.typ));
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rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ);
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rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ);
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rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ);
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rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ);
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/* Set Signal Polarity */
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val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0;
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rk_mipi_dsi_write(regs, HSYNC_ACTIVE_LOW, val);
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val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0;
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rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val);
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val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0;
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rk_mipi_dsi_write(regs, DATAEN_ACTIVE_LOW, val);
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val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0;
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rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val);
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/* Set video mode */
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rk_mipi_dsi_write(regs, CMD_VIDEO_MODE, VIDEO_MODE);
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/* Set video mode transmission type as burst mode */
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rk_mipi_dsi_write(regs, VID_MODE_TYPE, BURST_MODE);
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/* Set pix num in a video package */
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rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0);
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/* Set dpi color coding depth 24 bit */
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timing_node = ofnode_find_subnode(dev->node, "display-timings");
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node = ofnode_first_subnode(timing_node);
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val = ofnode_read_u32_default(node, "bits-per-pixel", -1);
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switch (val) {
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case 16:
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rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1);
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break;
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case 24:
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rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
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break;
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case 30:
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rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_30BIT);
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break;
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default:
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rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
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}
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/* Enable low power mode */
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rk_mipi_dsi_write(regs, LP_CMD_EN, 1);
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rk_mipi_dsi_write(regs, LP_HFP_EN, 1);
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rk_mipi_dsi_write(regs, LP_VACT_EN, 1);
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rk_mipi_dsi_write(regs, LP_VFP_EN, 1);
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rk_mipi_dsi_write(regs, LP_VBP_EN, 1);
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rk_mipi_dsi_write(regs, LP_VSA_EN, 1);
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/* Division for timeout counter clk */
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rk_mipi_dsi_write(regs, TO_CLK_DIVISION, 0x0a);
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/* Tx esc clk division from txbyte clk */
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rk_mipi_dsi_write(regs, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk);
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/* Timeout count for hs<->lp transation between Line period */
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rk_mipi_dsi_write(regs, HSTX_TO_CNT, 0x3e8);
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/* Phy State transfer timing */
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rk_mipi_dsi_write(regs, PHY_STOP_WAIT_TIME, 32);
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rk_mipi_dsi_write(regs, PHY_TXREQUESTCLKHS, 1);
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rk_mipi_dsi_write(regs, PHY_HS2LP_TIME, 0x14);
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rk_mipi_dsi_write(regs, PHY_LP2HS_TIME, 0x10);
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rk_mipi_dsi_write(regs, MAX_RD_TIME, 0x2710);
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/* Power on */
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rk_mipi_dsi_write(regs, SHUTDOWNZ, 1);
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return 0;
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}
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/* rk mipi dphy write function. It is used to write test data to dphy */
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static void rk_mipi_phy_write(uintptr_t regs, unsigned char test_code,
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unsigned char *test_data, unsigned char size)
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{
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int i = 0;
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/* Write Test code */
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rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
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rk_mipi_dsi_write(regs, PHY_TESTDIN, test_code);
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rk_mipi_dsi_write(regs, PHY_TESTEN, 1);
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rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
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rk_mipi_dsi_write(regs, PHY_TESTEN, 0);
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/* Write Test data */
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for (i = 0; i < size; i++) {
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rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
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rk_mipi_dsi_write(regs, PHY_TESTDIN, test_data[i]);
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rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
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}
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}
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/*
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* Mipi dphy config function. Calculate the suitable prediv, feedback div,
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* fsfreqrang value ,cap ,lpf and so on according to the given pix clk rate,
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* and then enable phy.
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*/
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int rk_mipi_phy_enable(struct udevice *dev)
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{
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int i;
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struct rk_mipi_priv *priv = dev_get_priv(dev);
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uintptr_t regs = priv->regs;
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u64 fbdiv;
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u64 prediv = 1;
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u32 max_fbdiv = 512;
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u32 max_prediv, min_prediv;
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u64 ddr_clk = priv->phy_clk;
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u32 refclk = priv->ref_clk;
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u32 remain = refclk;
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unsigned char test_data[2] = {0};
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int freq_rang[][2] = {
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{90, 0x01}, {100, 0x10}, {110, 0x20}, {130, 0x01},
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{140, 0x11}, {150, 0x21}, {170, 0x02}, {180, 0x12},
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{200, 0x22}, {220, 0x03}, {240, 0x13}, {250, 0x23},
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{270, 0x04}, {300, 0x14}, {330, 0x05}, {360, 0x15},
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{400, 0x25}, {450, 0x06}, {500, 0x16}, {550, 0x07},
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{600, 0x17}, {650, 0x08}, {700, 0x18}, {750, 0x09},
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{800, 0x19}, {850, 0x29}, {900, 0x39}, {950, 0x0a},
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{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
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{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
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{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
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};
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/* Shutdown mode */
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rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 0);
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rk_mipi_dsi_write(regs, PHY_RSTZ, 0);
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rk_mipi_dsi_write(regs, PHY_TESTCLR, 1);
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/* Pll locking */
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rk_mipi_dsi_write(regs, PHY_TESTCLR, 0);
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/* config cp and lfp */
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test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3;
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rk_mipi_phy_write(regs, CODE_PLL_VCORANGE_VCOCAP, test_data, 1);
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test_data[0] = 0x8;
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rk_mipi_phy_write(regs, CODE_PLL_CPCTRL, test_data, 1);
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test_data[0] = 0x80 | 0x40;
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rk_mipi_phy_write(regs, CODE_PLL_LPF_CP, test_data, 1);
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/* select the suitable value for fsfreqrang reg */
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for (i = 0; i < ARRAY_SIZE(freq_rang); i++) {
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if (ddr_clk / (MHz) <= freq_rang[i][0])
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break;
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}
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if (i == ARRAY_SIZE(freq_rang)) {
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debug("%s: Dphy freq out of range!\n", __func__);
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return -EINVAL;
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}
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test_data[0] = freq_rang[i][1] << 1;
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rk_mipi_phy_write(regs, CODE_HS_RX_LANE0, test_data, 1);
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/*
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* Calculate the best ddrclk and it's corresponding div value. If the
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* given pixelclock is great than 250M, ddrclk will be fix 1500M.
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* Otherwise,
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* it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz
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* according to spec.
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*/
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max_prediv = (refclk / (5 * MHz));
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min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1);
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debug("%s: DEBUG: max_prediv=%u, min_prediv=%u\n", __func__, max_prediv,
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min_prediv);
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if (max_prediv < min_prediv) {
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debug("%s: Invalid refclk value\n", __func__);
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return -EINVAL;
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}
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/* Calculate the best refclk and feedback division value for dphy pll */
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for (i = min_prediv; i < max_prediv; i++) {
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if ((ddr_clk * i % refclk < remain) &&
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(ddr_clk * i / refclk) < max_fbdiv) {
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prediv = i;
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remain = ddr_clk * i % refclk;
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}
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}
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fbdiv = ddr_clk * prediv / refclk;
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ddr_clk = refclk * fbdiv / prediv;
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priv->phy_clk = ddr_clk;
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debug("%s: DEBUG: refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n",
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__func__, refclk, prediv, fbdiv, ddr_clk);
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/* config prediv and feedback reg */
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test_data[0] = prediv - 1;
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rk_mipi_phy_write(regs, CODE_PLL_INPUT_DIV_RAT, test_data, 1);
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test_data[0] = (fbdiv - 1) & 0x1f;
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rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
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test_data[0] = (fbdiv - 1) >> 5 | 0x80;
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rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
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test_data[0] = 0x30;
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rk_mipi_phy_write(regs, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1);
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/* rest config */
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test_data[0] = 0x4d;
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rk_mipi_phy_write(regs, CODE_BANDGAP_BIAS_CTRL, test_data, 1);
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test_data[0] = 0x3d;
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rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
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test_data[0] = 0xdf;
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rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
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test_data[0] = 0x7;
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rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
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test_data[0] = 0x80 | 0x7;
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rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
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test_data[0] = 0x80 | 15;
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rk_mipi_phy_write(regs, CODE_HSTXDATALANEREQUSETSTATETIME,
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test_data, 1);
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test_data[0] = 0x80 | 85;
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rk_mipi_phy_write(regs, CODE_HSTXDATALANEPREPARESTATETIME,
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test_data, 1);
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test_data[0] = 0x40 | 10;
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rk_mipi_phy_write(regs, CODE_HSTXDATALANEHSZEROSTATETIME,
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test_data, 1);
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/* enter into stop mode */
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rk_mipi_dsi_write(regs, N_LANES, 0x03);
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rk_mipi_dsi_write(regs, PHY_ENABLECLK, 1);
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rk_mipi_dsi_write(regs, PHY_FORCEPLL, 1);
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rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 1);
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rk_mipi_dsi_write(regs, PHY_RSTZ, 1);
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return 0;
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}
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