mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-05 17:53:44 +09:00
c3d2c24f6c
In the case of booting from certain peripherals, such as UART, we must not see what the device descriptor says for RAW or FAT mode because in addition to being nonsensical, it leads to a hang. This is why we have a test currently for the boot mode being within range. The problem however is that on some platforms we get MMC2_2 as the boot mode and not the defined value for MMC2, and in others we get the value for MMC2_2. This is required to fix eMMC booting on omap5_uevm. Tested on am335x_evm (UART, NAND, SD), omap3_beagle (NAND, SD on classic, SD only on xM rev C5) and omap5_uevm (SD, eMMC). Signed-off-by: Tom Rini <trini@ti.com>
95 lines
2.7 KiB
ArmAsm
95 lines
2.7 KiB
ArmAsm
/*
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* Board specific setup info
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Author :
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* Aneesh V <aneesh@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/spl.h>
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#include <linux/linkage.h>
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ENTRY(save_boot_params)
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/*
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* See if the rom code passed pointer is valid:
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* It is not valid if it is not in non-secure SRAM
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* This may happen if you are booting with the help of
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* debugger
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*/
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ldr r2, =NON_SECURE_SRAM_START
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cmp r2, r0
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bgt 1f
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ldr r2, =NON_SECURE_SRAM_END
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cmp r2, r0
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blt 1f
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/*
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* store the boot params passed from rom code or saved
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* and passed by SPL
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*/
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cmp r0, #0
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beq 1f
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ldr r1, =boot_params
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str r0, [r1]
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#ifdef CONFIG_SPL_BUILD
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/* Store the boot device in spl_boot_device */
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ldrb r2, [r0, #BOOT_DEVICE_OFFSET] @ r1 <- value of boot device
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and r2, #BOOT_DEVICE_MASK
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ldr r3, =boot_params
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strb r2, [r3, #BOOT_DEVICE_OFFSET] @ spl_boot_device <- r1
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/*
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* boot mode is only valid for device that can be raw or FAT booted.
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* in other cases it may be fatal to look. While platforms differ
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* in the values used for each MMC slot, they are contiguous.
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*/
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cmp r2, #MMC_BOOT_DEVICES_START
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blt 2f
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cmp r2, #MMC_BOOT_DEVICES_END
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bgt 2f
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/* Store the boot mode (raw/FAT) in omap_bootmode */
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ldr r2, [r0, #DEV_DESC_PTR_OFFSET] @ get the device descriptor ptr
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ldr r2, [r2, #DEV_DATA_PTR_OFFSET] @ get the pDeviceData ptr
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ldr r2, [r2, #BOOT_MODE_OFFSET] @ get the boot mode
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ldr r3, =omap_bootmode
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str r2, [r3]
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#endif
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2:
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ldrb r2, [r0, #CH_FLAGS_OFFSET]
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ldr r3, =boot_params
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strb r2, [r3, #CH_FLAGS_OFFSET]
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1:
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bx lr
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ENDPROC(save_boot_params)
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ENTRY(set_pl310_ctrl_reg)
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PUSH {r4-r11, lr} @ save registers - ROM code may pollute
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@ our registers
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LDR r12, =0x102 @ Set PL310 control register - value in R0
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.word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5
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@ call ROM Code API to set control register
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POP {r4-r11, pc}
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ENDPROC(set_pl310_ctrl_reg)
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