mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-07 05:13:21 +09:00
![Stefan Roese](/assets/img/avatar_default.png)
Currently booting on A38x is broken. As the current code tries to detect the SoC family to disable the MMU for the A38x at runtime. But before the internal registers are switched to the new location (0xf100.0000), this runtime detection does not work. As all macros / defines are already assigned to the new location at 0xf100.0000. But the registers are sill mapped to the default location at 0xd000.0000. This patch now makes sure, no such runtime detection is used before the internal registers are configured to the new location. After this, the remaining cache cleanup is executed. Signed-off-by: Stefan Roese <sr@denx.de> Reported-by: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
426 lines
10 KiB
C
426 lines
10 KiB
C
/*
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* Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <ahci.h>
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#include <linux/mbus.h>
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#include <asm/io.h>
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#include <asm/pl310.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <sdhci.h>
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#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
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#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
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static struct mbus_win windows[] = {
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/* SPI */
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{ MBUS_SPI_BASE, MBUS_SPI_SIZE,
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_SPIFLASH },
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/* NOR */
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{ MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE,
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CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
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};
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void reset_cpu(unsigned long ignored)
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{
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struct mvebu_system_registers *reg =
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(struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
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writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
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writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
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while (1)
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;
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}
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int mvebu_soc_family(void)
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{
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u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
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if (devid == SOC_MV78460_ID)
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return MVEBU_SOC_AXP;
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if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
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devid == SOC_88F6828_ID)
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return MVEBU_SOC_A38X;
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return MVEBU_SOC_UNKNOWN;
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
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u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
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puts("SoC: ");
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switch (devid) {
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case SOC_MV78460_ID:
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puts("MV78460-");
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break;
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case SOC_88F6810_ID:
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puts("MV88F6810-");
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break;
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case SOC_88F6820_ID:
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puts("MV88F6820-");
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break;
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case SOC_88F6828_ID:
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puts("MV88F6828-");
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break;
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default:
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puts("Unknown-");
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break;
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}
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if (mvebu_soc_family() == MVEBU_SOC_AXP) {
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switch (revid) {
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case 1:
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puts("A0\n");
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break;
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case 2:
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puts("B0\n");
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break;
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default:
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printf("?? (%x)\n", revid);
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break;
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}
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}
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if (mvebu_soc_family() == MVEBU_SOC_A38X) {
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switch (revid) {
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case MV_88F68XX_Z1_ID:
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puts("Z1\n");
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break;
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case MV_88F68XX_A0_ID:
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puts("A0\n");
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break;
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default:
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printf("?? (%x)\n", revid);
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break;
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}
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}
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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/*
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* This function initialize Controller DRAM Fastpath windows.
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* It takes the CS size information from the 0x1500 scratch registers
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* and sets the correct windows sizes and base addresses accordingly.
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*
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* These values are set in the scratch registers by the Marvell
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* DDR3 training code, which is executed by the BootROM before the
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* main payload (U-Boot) is executed. This training code is currently
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* only available in the Marvell U-Boot version. It needs to be
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* ported to mainline U-Boot SPL at some point.
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*/
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static void update_sdram_window_sizes(void)
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{
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u64 base = 0;
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u32 size, temp;
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int i;
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for (i = 0; i < SDRAM_MAX_CS; i++) {
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size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
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if (size != 0) {
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size |= ~(SDRAM_ADDR_MASK);
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/* Set Base Address */
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temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
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writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
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/*
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* Check if out of max window size and resize
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* the window
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*/
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temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
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~(SDRAM_ADDR_MASK)) | 1;
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temp |= (size & SDRAM_ADDR_MASK);
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writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
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base += ((u64)size + 1);
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} else {
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/*
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* Disable window if not used, otherwise this
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* leads to overlapping enabled windows with
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* pretty strange results
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*/
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clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
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}
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}
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}
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void mmu_disable(void)
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{
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asm volatile(
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"mrc p15, 0, r0, c1, c0, 0\n"
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"bic r0, #1\n"
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"mcr p15, 0, r0, c1, c0, 0\n");
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}
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#ifdef CONFIG_ARCH_CPU_INIT
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static void set_cbar(u32 addr)
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{
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asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
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}
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#define MV_USB_PHY_BASE (MVEBU_AXP_USB_BASE + 0x800)
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#define MV_USB_PHY_PLL_REG(reg) (MV_USB_PHY_BASE | (((reg) & 0xF) << 2))
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#define MV_USB_X3_BASE(addr) (MVEBU_AXP_USB_BASE | BIT(11) | \
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(((addr) & 0xF) << 6))
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#define MV_USB_X3_PHY_CHANNEL(dev, reg) (MV_USB_X3_BASE((dev) + 1) | \
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(((reg) & 0xF) << 2))
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static void setup_usb_phys(void)
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{
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int dev;
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/*
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* USB PLL init
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*/
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/* Setup PLL frequency */
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/* USB REF frequency = 25 MHz */
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clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0x3ff, 0x605);
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/* Power up PLL and PHY channel */
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clrsetbits_le32(MV_USB_PHY_PLL_REG(2), 0, BIT(9));
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/* Assert VCOCAL_START */
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clrsetbits_le32(MV_USB_PHY_PLL_REG(1), 0, BIT(21));
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mdelay(1);
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/*
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* USB PHY init (change from defaults) specific for 40nm (78X30 78X60)
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*/
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for (dev = 0; dev < 3; dev++) {
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clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 3), 0, BIT(15));
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/* Assert REG_RCAL_START in channel REG 1 */
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clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), 0, BIT(12));
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udelay(40);
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clrsetbits_le32(MV_USB_X3_PHY_CHANNEL(dev, 1), BIT(12), 0);
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}
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}
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int arch_cpu_init(void)
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{
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMADA_38X)
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/*
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* Only with disabled MMU its possible to switch the base
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* register address on Armada 38x. Without this the SDRAM
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* located at >= 0x4000.0000 is also not accessible, as its
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* still locked to cache.
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*/
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mmu_disable();
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#endif
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/* Linux expects the internal registers to be at 0xf1000000 */
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writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
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set_cbar(SOC_REGS_PHY_BASE + 0xC000);
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#if !defined(CONFIG_SPL_BUILD)
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/*
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* From this stage on, the SoC detection is working. As we have
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* configured the internal register base to the value used
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* in the macros / defines in the U-Boot header (soc.h).
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*/
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if (mvebu_soc_family() == MVEBU_SOC_A38X) {
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struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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/*
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* To fully release / unlock this area from cache, we need
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* to flush all caches and disable the L2 cache.
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*/
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icache_disable();
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dcache_disable();
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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#endif
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/*
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* We need to call mvebu_mbus_probe() before calling
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* update_sdram_window_sizes() as it disables all previously
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* configured mbus windows and then configures them as
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* required for U-Boot. Calling update_sdram_window_sizes()
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* without this configuration will not work, as the internal
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* registers can't be accessed reliably because of potenial
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* double mapping.
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* After updating the SDRAM access windows we need to call
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* mvebu_mbus_probe() again, as this now correctly configures
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* the SDRAM areas that are later used by the MVEBU drivers
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* (e.g. USB, NETA).
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*/
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/*
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* First disable all windows
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*/
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mvebu_mbus_probe(NULL, 0);
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if (mvebu_soc_family() == MVEBU_SOC_AXP) {
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/*
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* Now the SDRAM access windows can be reconfigured using
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* the information in the SDRAM scratch pad registers
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*/
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update_sdram_window_sizes();
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}
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/*
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* Finally the mbus windows can be configured with the
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* updated SDRAM sizes
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*/
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mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
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if (mvebu_soc_family() == MVEBU_SOC_AXP) {
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/* Enable GBE0, GBE1, LCD and NFC PUP */
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clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0,
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GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN |
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NAND_PUP_EN | SPI_PUP_EN);
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/* Configure USB PLL and PHYs on AXP */
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setup_usb_phys();
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}
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/* Enable NAND and NAND arbiter */
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clrsetbits_le32(MVEBU_SOC_DEV_MUX_REG, 0, NAND_EN | NAND_ARBITER_EN);
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/* Disable MBUS error propagation */
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clrsetbits_le32(SOC_COHERENCY_FABRIC_CTRL_REG, MBUS_ERR_PROP_EN, 0);
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return 0;
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}
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#endif /* CONFIG_ARCH_CPU_INIT */
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u32 mvebu_get_nand_clock(void)
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{
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return CONFIG_SYS_MVEBU_PLL_CLOCK /
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((readl(MVEBU_CORE_DIV_CLK_CTRL(1)) &
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NAND_ECC_DIVCKL_RATIO_MASK) >> NAND_ECC_DIVCKL_RATIO_OFFS);
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}
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/*
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* SOC specific misc init
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*/
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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/* Nothing yet, perhaps we need something here later */
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return 0;
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}
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#endif /* CONFIG_ARCH_MISC_INIT */
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#ifdef CONFIG_MVNETA
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int cpu_eth_init(bd_t *bis)
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{
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u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
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MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
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u8 phy_addr[] = CONFIG_PHY_ADDR;
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int i;
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/*
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* Only Armada XP supports all 4 ethernet interfaces. A38x has
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* slightly different base addresses for its 2-3 interfaces.
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*/
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if (mvebu_soc_family() != MVEBU_SOC_AXP) {
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enet_base[1] = MVEBU_EGIGA2_BASE;
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enet_base[2] = MVEBU_EGIGA3_BASE;
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}
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for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
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mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
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return 0;
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}
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#endif
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#ifdef CONFIG_MV_SDHCI
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int board_mmc_init(bd_t *bis)
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{
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mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
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SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
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return 0;
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}
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#endif
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#ifdef CONFIG_SCSI_AHCI_PLAT
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#define AHCI_VENDOR_SPECIFIC_0_ADDR 0xa0
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#define AHCI_VENDOR_SPECIFIC_0_DATA 0xa4
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#define AHCI_WINDOW_CTRL(win) (0x60 + ((win) << 4))
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#define AHCI_WINDOW_BASE(win) (0x64 + ((win) << 4))
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#define AHCI_WINDOW_SIZE(win) (0x68 + ((win) << 4))
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static void ahci_mvebu_mbus_config(void __iomem *base)
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{
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const struct mbus_dram_target_info *dram;
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int i;
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dram = mvebu_mbus_dram_info();
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for (i = 0; i < 4; i++) {
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writel(0, base + AHCI_WINDOW_CTRL(i));
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writel(0, base + AHCI_WINDOW_BASE(i));
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writel(0, base + AHCI_WINDOW_SIZE(i));
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}
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for (i = 0; i < dram->num_cs; i++) {
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const struct mbus_dram_window *cs = dram->cs + i;
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writel((cs->mbus_attr << 8) |
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(dram->mbus_dram_target_id << 4) | 1,
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base + AHCI_WINDOW_CTRL(i));
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writel(cs->base >> 16, base + AHCI_WINDOW_BASE(i));
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writel(((cs->size - 1) & 0xffff0000),
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base + AHCI_WINDOW_SIZE(i));
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}
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}
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static void ahci_mvebu_regret_option(void __iomem *base)
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{
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/*
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* Enable the regret bit to allow the SATA unit to regret a
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* request that didn't receive an acknowlegde and avoid a
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* deadlock
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*/
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writel(0x4, base + AHCI_VENDOR_SPECIFIC_0_ADDR);
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writel(0x80, base + AHCI_VENDOR_SPECIFIC_0_DATA);
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}
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void scsi_init(void)
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{
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printf("MVEBU SATA INIT\n");
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ahci_mvebu_mbus_config((void __iomem *)MVEBU_SATA0_BASE);
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ahci_mvebu_regret_option((void __iomem *)MVEBU_SATA0_BASE);
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ahci_init((void __iomem *)MVEBU_SATA0_BASE);
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}
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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/* First disable L2 cache - may still be enable from BootROM */
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if (mvebu_soc_family() == MVEBU_SOC_A38X)
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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/* Avoid problem with e.g. neta ethernet driver */
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invalidate_dcache_all();
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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