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https://github.com/brain-hackers/u-boot-brain
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fd6e0b0525
This patch add a new SPI driver for MSCC SOCs that does not sport the designware SPI hardware controller. Performance gain: 7.664 seconds vs. 17.633 for 1 Mbyte write. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
89 lines
2.0 KiB
C
89 lines
2.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2018 Microsemi Corporation
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*/
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#ifndef __ASM_MACH_COMMON_H
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#define __ASM_MACH_COMMON_H
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#if defined(CONFIG_SOC_OCELOT)
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#include <mach/ocelot/ocelot.h>
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#include <mach/ocelot/ocelot_devcpu_gcb.h>
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#include <mach/ocelot/ocelot_devcpu_gcb_miim_regs.h>
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#include <mach/ocelot/ocelot_icpu_cfg.h>
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#elif defined(CONFIG_SOC_LUTON)
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#include <mach/luton/luton.h>
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#include <mach/luton/luton_devcpu_gcb.h>
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#include <mach/luton/luton_devcpu_gcb_miim_regs.h>
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#include <mach/luton/luton_icpu_cfg.h>
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#else
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#error Unsupported platform
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#endif
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#define MSCC_DDR_TO 0x20000000 /* DDR RAM base offset */
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#define MSCC_MEMCTL1_TO 0x40000000 /* SPI/PI base offset */
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#define MSCC_MEMCTL2_TO 0x50000000 /* SPI/PI base offset */
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#define MSCC_FLASH_TO MSCC_MEMCTL1_TO /* Flash base offset */
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#define VCOREIII_TIMER_DIVIDER 25 /* Clock tick ~ 0.1 us */
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/* Common utility functions */
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/*
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* Perform a number of NOP instructions, blocks of 8 instructions.
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* The (inlined) function will not affect cache or processor state.
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*/
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static inline void mscc_vcoreiii_nop_delay(int delay)
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{
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while (delay > 0) {
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#define DELAY_8_NOPS() asm volatile("nop; nop; nop; nop; nop; nop; nop; nop;")
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switch (delay) {
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case 8:
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DELAY_8_NOPS();
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/* fallthrough */
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case 7:
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DELAY_8_NOPS();
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/* fallthrough */
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case 6:
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DELAY_8_NOPS();
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/* fallthrough */
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case 5:
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DELAY_8_NOPS();
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/* fallthrough */
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case 4:
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DELAY_8_NOPS();
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/* fallthrough */
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case 3:
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DELAY_8_NOPS();
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/* fallthrough */
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case 2:
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DELAY_8_NOPS();
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/* fallthrough */
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case 1:
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DELAY_8_NOPS();
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}
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delay -= 8;
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#undef DELAY_8_NOPS
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}
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}
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int mscc_phy_rd_wr(u8 read,
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u32 miim_controller,
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u8 miim_addr,
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u8 addr,
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u16 *value);
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int mscc_phy_rd(u32 miim_controller,
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u8 miim_addr,
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u8 addr,
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u16 *value);
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int mscc_phy_wr(u32 miim_controller,
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u8 miim_addr,
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u8 addr,
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u16 value);
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void mscc_gpio_set_alternate(int gpio, int mode);
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#endif /* __ASM_MACH_COMMON_H */
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