mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 09:58:52 +09:00
![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
622 lines
16 KiB
C
622 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Samsung Electronics
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*
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* Author: InKi Dae <inki.dae@samsung.com>
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* Author: Donghwa Lee <dh09.lee@samsung.com>
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*/
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#include <common.h>
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#include <lcd.h>
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#include <log.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <asm/arch/dsim.h>
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#include <asm/arch/mipi_dsim.h>
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#include "exynos_mipi_dsi_lowlevel.h"
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#define MHZ (1000 * 1000)
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#define FIN_HZ (24 * MHZ)
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#define DFIN_PLL_MIN_HZ (6 * MHZ)
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#define DFIN_PLL_MAX_HZ (12 * MHZ)
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#define DFVCO_MIN_HZ (500 * MHZ)
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#define DFVCO_MAX_HZ (1000 * MHZ)
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#define TRY_GET_FIFO_TIMEOUT (5000 * 2)
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/* MIPI-DSIM status types. */
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enum {
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DSIM_STATE_INIT, /* should be initialized. */
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DSIM_STATE_STOP, /* CPU and LCDC are LP mode. */
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DSIM_STATE_HSCLKEN, /* HS clock was enabled. */
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DSIM_STATE_ULPS
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};
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/* define DSI lane types. */
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enum {
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DSIM_LANE_CLOCK = (1 << 0),
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DSIM_LANE_DATA0 = (1 << 1),
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DSIM_LANE_DATA1 = (1 << 2),
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DSIM_LANE_DATA2 = (1 << 3),
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DSIM_LANE_DATA3 = (1 << 4)
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};
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static unsigned int dpll_table[15] = {
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100, 120, 170, 220, 270,
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320, 390, 450, 510, 560,
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640, 690, 770, 870, 950
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};
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static void exynos_mipi_dsi_long_data_wr(struct mipi_dsim_device *dsim,
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const unsigned char *data0, unsigned int data1)
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{
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unsigned int data_cnt = 0, payload = 0;
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/* in case that data count is more then 4 */
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for (data_cnt = 0; data_cnt < data1; data_cnt += 4) {
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/*
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* after sending 4bytes per one time,
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* send remainder data less then 4.
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*/
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if ((data1 - data_cnt) < 4) {
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if ((data1 - data_cnt) == 3) {
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payload = data0[data_cnt] |
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data0[data_cnt + 1] << 8 |
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data0[data_cnt + 2] << 16;
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debug("count = 3 payload = %x, %x %x %x\n",
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payload, data0[data_cnt],
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data0[data_cnt + 1],
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data0[data_cnt + 2]);
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} else if ((data1 - data_cnt) == 2) {
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payload = data0[data_cnt] |
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data0[data_cnt + 1] << 8;
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debug("count = 2 payload = %x, %x %x\n", payload,
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data0[data_cnt], data0[data_cnt + 1]);
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} else if ((data1 - data_cnt) == 1) {
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payload = data0[data_cnt];
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}
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} else {
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/* send 4bytes per one time. */
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payload = data0[data_cnt] |
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data0[data_cnt + 1] << 8 |
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data0[data_cnt + 2] << 16 |
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data0[data_cnt + 3] << 24;
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debug("count = 4 payload = %x, %x %x %x %x\n",
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payload, *(u8 *)(data0 + data_cnt),
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data0[data_cnt + 1],
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data0[data_cnt + 2],
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data0[data_cnt + 3]);
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}
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exynos_mipi_dsi_wr_tx_data(dsim, payload);
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}
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}
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int exynos_mipi_dsi_wr_data(struct mipi_dsim_device *dsim, unsigned int data_id,
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const unsigned char *data0, unsigned int data1)
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{
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unsigned int timeout = TRY_GET_FIFO_TIMEOUT;
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unsigned long delay_val, delay;
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unsigned int check_rx_ack = 0;
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if (dsim->state == DSIM_STATE_ULPS) {
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debug("state is ULPS.\n");
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return -EINVAL;
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}
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delay_val = MHZ / dsim->dsim_config->esc_clk;
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delay = 10 * delay_val;
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mdelay(delay);
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/* only if transfer mode is LPDT, wait SFR becomes empty. */
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if (dsim->state == DSIM_STATE_STOP) {
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while (!(exynos_mipi_dsi_get_fifo_state(dsim) &
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SFR_HEADER_EMPTY)) {
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if ((timeout--) > 0)
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mdelay(1);
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else {
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debug("SRF header fifo is not empty.\n");
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return -EINVAL;
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}
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}
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}
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switch (data_id) {
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/* short packet types of packet types for command. */
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case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
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case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
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case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
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case MIPI_DSI_DCS_SHORT_WRITE:
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case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
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case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
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debug("data0 = %x data1 = %x\n",
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data0[0], data0[1]);
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exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
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if (check_rx_ack) {
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/* process response func should be implemented */
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return 0;
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} else {
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return -EINVAL;
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}
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/* general command */
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case MIPI_DSI_COLOR_MODE_OFF:
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case MIPI_DSI_COLOR_MODE_ON:
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case MIPI_DSI_SHUTDOWN_PERIPHERAL:
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case MIPI_DSI_TURN_ON_PERIPHERAL:
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exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
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if (check_rx_ack) {
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/* process response func should be implemented. */
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return 0;
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} else {
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return -EINVAL;
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}
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/* packet types for video data */
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case MIPI_DSI_V_SYNC_START:
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case MIPI_DSI_V_SYNC_END:
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case MIPI_DSI_H_SYNC_START:
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case MIPI_DSI_H_SYNC_END:
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case MIPI_DSI_END_OF_TRANSMISSION:
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return 0;
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/* short and response packet types for command */
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case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM:
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case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM:
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case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM:
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case MIPI_DSI_DCS_READ:
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exynos_mipi_dsi_clear_all_interrupt(dsim);
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exynos_mipi_dsi_wr_tx_header(dsim, data_id, data0[0], data0[1]);
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/* process response func should be implemented. */
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return 0;
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/* long packet type and null packet */
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case MIPI_DSI_NULL_PACKET:
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case MIPI_DSI_BLANKING_PACKET:
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return 0;
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case MIPI_DSI_GENERIC_LONG_WRITE:
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case MIPI_DSI_DCS_LONG_WRITE:
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{
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unsigned int payload = 0;
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/* if data count is less then 4, then send 3bytes data. */
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if (data1 < 4) {
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payload = data0[0] |
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data0[1] << 8 |
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data0[2] << 16;
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exynos_mipi_dsi_wr_tx_data(dsim, payload);
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debug("count = %d payload = %x,%x %x %x\n",
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data1, payload, data0[0],
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data0[1], data0[2]);
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} else {
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/* in case that data count is more then 4 */
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exynos_mipi_dsi_long_data_wr(dsim, data0, data1);
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}
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/* put data into header fifo */
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exynos_mipi_dsi_wr_tx_header(dsim, data_id, data1 & 0xff,
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(data1 & 0xff00) >> 8);
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}
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if (check_rx_ack)
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/* process response func should be implemented. */
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return 0;
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else
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return -EINVAL;
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/* packet typo for video data */
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case MIPI_DSI_PACKED_PIXEL_STREAM_16:
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case MIPI_DSI_PACKED_PIXEL_STREAM_18:
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case MIPI_DSI_PIXEL_STREAM_3BYTE_18:
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case MIPI_DSI_PACKED_PIXEL_STREAM_24:
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if (check_rx_ack) {
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/* process response func should be implemented. */
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return 0;
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} else {
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return -EINVAL;
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}
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default:
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debug("data id %x is not supported current DSI spec.\n",
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data_id);
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return -EINVAL;
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}
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return 0;
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}
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int exynos_mipi_dsi_pll_on(struct mipi_dsim_device *dsim, unsigned int enable)
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{
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int sw_timeout;
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if (enable) {
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sw_timeout = 1000;
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exynos_mipi_dsi_clear_interrupt(dsim);
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exynos_mipi_dsi_enable_pll(dsim, 1);
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while (1) {
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sw_timeout--;
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if (exynos_mipi_dsi_is_pll_stable(dsim))
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return 0;
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if (sw_timeout == 0)
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return -EINVAL;
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}
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} else
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exynos_mipi_dsi_enable_pll(dsim, 0);
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return 0;
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}
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unsigned long exynos_mipi_dsi_change_pll(struct mipi_dsim_device *dsim,
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unsigned int pre_divider, unsigned int main_divider,
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unsigned int scaler)
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{
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unsigned long dfin_pll, dfvco, dpll_out;
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unsigned int i, freq_band = 0xf;
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dfin_pll = (FIN_HZ / pre_divider);
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/******************************************************
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* Serial Clock(=ByteClk X 8) FreqBand[3:0] *
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******************************************************
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* ~ 99.99 MHz 0000
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* 100 ~ 119.99 MHz 0001
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* 120 ~ 159.99 MHz 0010
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* 160 ~ 199.99 MHz 0011
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* 200 ~ 239.99 MHz 0100
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* 140 ~ 319.99 MHz 0101
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* 320 ~ 389.99 MHz 0110
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* 390 ~ 449.99 MHz 0111
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* 450 ~ 509.99 MHz 1000
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* 510 ~ 559.99 MHz 1001
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* 560 ~ 639.99 MHz 1010
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* 640 ~ 689.99 MHz 1011
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* 690 ~ 769.99 MHz 1100
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* 770 ~ 869.99 MHz 1101
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* 870 ~ 949.99 MHz 1110
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* 950 ~ 1000 MHz 1111
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******************************************************/
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if (dfin_pll < DFIN_PLL_MIN_HZ || dfin_pll > DFIN_PLL_MAX_HZ) {
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debug("fin_pll range should be 6MHz ~ 12MHz\n");
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exynos_mipi_dsi_enable_afc(dsim, 0, 0);
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} else {
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if (dfin_pll < 7 * MHZ)
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exynos_mipi_dsi_enable_afc(dsim, 1, 0x1);
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else if (dfin_pll < 8 * MHZ)
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exynos_mipi_dsi_enable_afc(dsim, 1, 0x0);
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else if (dfin_pll < 9 * MHZ)
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exynos_mipi_dsi_enable_afc(dsim, 1, 0x3);
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else if (dfin_pll < 10 * MHZ)
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exynos_mipi_dsi_enable_afc(dsim, 1, 0x2);
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else if (dfin_pll < 11 * MHZ)
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exynos_mipi_dsi_enable_afc(dsim, 1, 0x5);
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else
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exynos_mipi_dsi_enable_afc(dsim, 1, 0x4);
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}
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dfvco = dfin_pll * main_divider;
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debug("dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
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dfvco, dfin_pll, main_divider);
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if (dfvco < DFVCO_MIN_HZ || dfvco > DFVCO_MAX_HZ)
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debug("fvco range should be 500MHz ~ 1000MHz\n");
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dpll_out = dfvco / (1 << scaler);
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debug("dpll_out = %lu, dfvco = %lu, scaler = %d\n",
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dpll_out, dfvco, scaler);
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for (i = 0; i < ARRAY_SIZE(dpll_table); i++) {
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if (dpll_out < dpll_table[i] * MHZ) {
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freq_band = i;
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break;
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}
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}
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debug("freq_band = %d\n", freq_band);
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exynos_mipi_dsi_pll_freq(dsim, pre_divider, main_divider, scaler);
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exynos_mipi_dsi_hs_zero_ctrl(dsim, 0);
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exynos_mipi_dsi_prep_ctrl(dsim, 0);
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/* Freq Band */
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exynos_mipi_dsi_pll_freq_band(dsim, freq_band);
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/* Stable time */
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exynos_mipi_dsi_pll_stable_time(dsim,
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dsim->dsim_config->pll_stable_time);
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/* Enable PLL */
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debug("FOUT of mipi dphy pll is %luMHz\n",
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(dpll_out / MHZ));
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return dpll_out;
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}
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int exynos_mipi_dsi_set_clock(struct mipi_dsim_device *dsim,
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unsigned int byte_clk_sel, unsigned int enable)
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{
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unsigned int esc_div;
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unsigned long esc_clk_error_rate;
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unsigned long hs_clk = 0, byte_clk = 0, escape_clk = 0;
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if (enable) {
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dsim->e_clk_src = byte_clk_sel;
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/* Escape mode clock and byte clock source */
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exynos_mipi_dsi_set_byte_clock_src(dsim, byte_clk_sel);
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/* DPHY, DSIM Link : D-PHY clock out */
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if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
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hs_clk = exynos_mipi_dsi_change_pll(dsim,
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dsim->dsim_config->p, dsim->dsim_config->m,
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dsim->dsim_config->s);
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if (hs_clk == 0) {
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debug("failed to get hs clock.\n");
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return -EINVAL;
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}
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byte_clk = hs_clk / 8;
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exynos_mipi_dsi_enable_pll_bypass(dsim, 0);
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exynos_mipi_dsi_pll_on(dsim, 1);
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/* DPHY : D-PHY clock out, DSIM link : external clock out */
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} else if (byte_clk_sel == DSIM_EXT_CLK_DIV8)
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debug("not support EXT CLK source for MIPI DSIM\n");
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else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS)
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debug("not support EXT CLK source for MIPI DSIM\n");
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/* escape clock divider */
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esc_div = byte_clk / (dsim->dsim_config->esc_clk);
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debug("esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
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esc_div, byte_clk, dsim->dsim_config->esc_clk);
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if ((byte_clk / esc_div) >= (20 * MHZ) ||
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(byte_clk / esc_div) > dsim->dsim_config->esc_clk)
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esc_div += 1;
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escape_clk = byte_clk / esc_div;
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debug("escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
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escape_clk, byte_clk, esc_div);
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/* enable escape clock. */
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exynos_mipi_dsi_enable_byte_clock(dsim, 1);
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/* enable byte clk and escape clock */
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exynos_mipi_dsi_set_esc_clk_prs(dsim, 1, esc_div);
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/* escape clock on lane */
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exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
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(DSIM_LANE_CLOCK | dsim->data_lane), 1);
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debug("byte clock is %luMHz\n",
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(byte_clk / MHZ));
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debug("escape clock that user's need is %lu\n",
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(dsim->dsim_config->esc_clk / MHZ));
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debug("escape clock divider is %x\n", esc_div);
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debug("escape clock is %luMHz\n",
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((byte_clk / esc_div) / MHZ));
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if ((byte_clk / esc_div) > escape_clk) {
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esc_clk_error_rate = escape_clk /
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(byte_clk / esc_div);
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debug("error rate is %lu over.\n",
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(esc_clk_error_rate / 100));
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} else if ((byte_clk / esc_div) < (escape_clk)) {
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esc_clk_error_rate = (byte_clk / esc_div) /
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escape_clk;
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debug("error rate is %lu under.\n",
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(esc_clk_error_rate / 100));
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}
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} else {
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exynos_mipi_dsi_enable_esc_clk_on_lane(dsim,
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(DSIM_LANE_CLOCK | dsim->data_lane), 0);
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exynos_mipi_dsi_set_esc_clk_prs(dsim, 0, 0);
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/* disable escape clock. */
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exynos_mipi_dsi_enable_byte_clock(dsim, 0);
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if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
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exynos_mipi_dsi_pll_on(dsim, 0);
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}
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return 0;
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}
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int exynos_mipi_dsi_init_dsim(struct mipi_dsim_device *dsim)
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{
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dsim->state = DSIM_STATE_INIT;
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switch (dsim->dsim_config->e_no_data_lane) {
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case DSIM_DATA_LANE_1:
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dsim->data_lane = DSIM_LANE_DATA0;
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break;
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case DSIM_DATA_LANE_2:
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dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
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break;
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case DSIM_DATA_LANE_3:
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dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
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DSIM_LANE_DATA2;
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break;
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case DSIM_DATA_LANE_4:
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dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
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DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
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break;
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default:
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debug("data lane is invalid.\n");
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return -EINVAL;
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};
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exynos_mipi_dsi_sw_reset(dsim);
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|
exynos_mipi_dsi_dp_dn_swap(dsim, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int exynos_mipi_dsi_enable_frame_done_int(struct mipi_dsim_device *dsim,
|
|
unsigned int enable)
|
|
{
|
|
/* enable only frame done interrupt */
|
|
exynos_mipi_dsi_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void convert_to_fb_videomode(struct fb_videomode *mode1,
|
|
struct vidinfo *mode2)
|
|
{
|
|
mode1->xres = mode2->vl_width;
|
|
mode1->yres = mode2->vl_height;
|
|
mode1->upper_margin = mode2->vl_vfpd;
|
|
mode1->lower_margin = mode2->vl_vbpd;
|
|
mode1->left_margin = mode2->vl_hfpd;
|
|
mode1->right_margin = mode2->vl_hbpd;
|
|
mode1->vsync_len = mode2->vl_vspw;
|
|
mode1->hsync_len = mode2->vl_hspw;
|
|
}
|
|
|
|
int exynos_mipi_dsi_set_display_mode(struct mipi_dsim_device *dsim,
|
|
struct mipi_dsim_config *dsim_config)
|
|
{
|
|
struct exynos_platform_mipi_dsim *dsim_pd;
|
|
struct fb_videomode lcd_video;
|
|
struct vidinfo *vid;
|
|
|
|
dsim_pd = (struct exynos_platform_mipi_dsim *)dsim->pd;
|
|
vid = (struct vidinfo *)dsim_pd->lcd_panel_info;
|
|
|
|
convert_to_fb_videomode(&lcd_video, vid);
|
|
|
|
/* in case of VIDEO MODE (RGB INTERFACE), it sets polarities. */
|
|
if (dsim->dsim_config->e_interface == (u32) DSIM_VIDEO) {
|
|
if (dsim->dsim_config->auto_vertical_cnt == 0) {
|
|
exynos_mipi_dsi_set_main_disp_vporch(dsim,
|
|
vid->vl_cmd_allow_len,
|
|
lcd_video.upper_margin,
|
|
lcd_video.lower_margin);
|
|
exynos_mipi_dsi_set_main_disp_hporch(dsim,
|
|
lcd_video.left_margin,
|
|
lcd_video.right_margin);
|
|
exynos_mipi_dsi_set_main_disp_sync_area(dsim,
|
|
lcd_video.vsync_len,
|
|
lcd_video.hsync_len);
|
|
}
|
|
}
|
|
|
|
exynos_mipi_dsi_set_main_disp_resol(dsim, lcd_video.xres,
|
|
lcd_video.yres);
|
|
|
|
exynos_mipi_dsi_display_config(dsim, dsim->dsim_config);
|
|
|
|
debug("lcd panel ==> width = %d, height = %d\n",
|
|
lcd_video.xres, lcd_video.yres);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int exynos_mipi_dsi_init_link(struct mipi_dsim_device *dsim)
|
|
{
|
|
unsigned int time_out = 100;
|
|
|
|
switch (dsim->state) {
|
|
case DSIM_STATE_INIT:
|
|
exynos_mipi_dsi_init_fifo_pointer(dsim, 0x1f);
|
|
|
|
/* dsi configuration */
|
|
exynos_mipi_dsi_init_config(dsim);
|
|
exynos_mipi_dsi_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
|
|
exynos_mipi_dsi_enable_lane(dsim, dsim->data_lane, 1);
|
|
|
|
/* set clock configuration */
|
|
exynos_mipi_dsi_set_clock(dsim,
|
|
dsim->dsim_config->e_byte_clk, 1);
|
|
|
|
/* check clock and data lane state are stop state */
|
|
while (!(exynos_mipi_dsi_is_lane_state(dsim))) {
|
|
time_out--;
|
|
if (time_out == 0) {
|
|
debug("DSI Master is not stop state.\n");
|
|
debug("Check initialization process\n");
|
|
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
dsim->state = DSIM_STATE_STOP;
|
|
|
|
/* BTA sequence counters */
|
|
exynos_mipi_dsi_set_stop_state_counter(dsim,
|
|
dsim->dsim_config->stop_holding_cnt);
|
|
exynos_mipi_dsi_set_bta_timeout(dsim,
|
|
dsim->dsim_config->bta_timeout);
|
|
exynos_mipi_dsi_set_lpdr_timeout(dsim,
|
|
dsim->dsim_config->rx_timeout);
|
|
|
|
return 0;
|
|
default:
|
|
debug("DSI Master is already init.\n");
|
|
return 0;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int exynos_mipi_dsi_set_hs_enable(struct mipi_dsim_device *dsim)
|
|
{
|
|
if (dsim->state == DSIM_STATE_STOP) {
|
|
if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
|
|
dsim->state = DSIM_STATE_HSCLKEN;
|
|
|
|
/* set LCDC and CPU transfer mode to HS. */
|
|
exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
|
|
exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
|
|
|
|
exynos_mipi_dsi_enable_hs_clock(dsim, 1);
|
|
|
|
return 0;
|
|
} else
|
|
debug("clock source is external bypass.\n");
|
|
} else
|
|
debug("DSIM is not stop state.\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
int exynos_mipi_dsi_set_data_transfer_mode(struct mipi_dsim_device *dsim,
|
|
unsigned int mode)
|
|
{
|
|
if (mode) {
|
|
if (dsim->state != DSIM_STATE_HSCLKEN) {
|
|
debug("HS Clock lane is not enabled.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
exynos_mipi_dsi_set_lcdc_transfer_mode(dsim, 0);
|
|
} else {
|
|
if (dsim->state == DSIM_STATE_INIT || dsim->state ==
|
|
DSIM_STATE_ULPS) {
|
|
debug("DSI Master is not STOP or HSDT state.\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
exynos_mipi_dsi_set_cpu_transfer_mode(dsim, 0);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int exynos_mipi_dsi_get_frame_done_status(struct mipi_dsim_device *dsim)
|
|
{
|
|
return _exynos_mipi_dsi_get_frame_done_status(dsim);
|
|
}
|
|
|
|
int exynos_mipi_dsi_clear_frame_done(struct mipi_dsim_device *dsim)
|
|
{
|
|
_exynos_mipi_dsi_clear_frame_done(dsim);
|
|
|
|
return 0;
|
|
}
|