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9c77cb73c7
Added pin control support in device tree for zynqmp. Signed-off-by: Chirag Parekh <chirag.parekh@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
31 lines
919 B
C
31 lines
919 B
C
/*
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* MIO pin configuration defines for Xilinx ZynqMP
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*
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* Copyright (C) 2017 Xilinx, Inc.
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* Author: Chirag Parekh <chirag.parekh@xilinx.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
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#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
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/* Bit value for IO standards */
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#define IO_STANDARD_LVCMOS33 0
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#define IO_STANDARD_LVCMOS18 1
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/* Bit values for Slew Rates */
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#define SLEW_RATE_FAST 0
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#define SLEW_RATE_SLOW 1
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/* Bit values for Pin inputs */
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#define PIN_INPUT_TYPE_CMOS 0
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#define PIN_INPUT_TYPE_SCHMITT 1
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#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
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