mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
96d2bb952b
Booke does not require exception vectors to be located at address zero. U-Boot was doing so anyway, simply because that's how it had been done on other PPC. The downside of this is that once the OS is loaded to address zero, the exception vectors have been overwritten -- which makes it difficult to diagnose a crash that happens after that point. The IVOR setup and trap entry code is simplified somewhat as a result. Also, there is no longer a need to align individual exceptions on 0x100 byte boundaries. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
68 lines
1.8 KiB
C
68 lines
1.8 KiB
C
/*
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* Copyright 2004, 2007 Freescale Semiconductor.
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* Copyright(c) 2003 Motorola Inc.
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*/
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#ifndef __MPC85xx_H__
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#define __MPC85xx_H__
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#if defined(CONFIG_E500)
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#include <e500.h>
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#endif
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/*
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* SCCR - System Clock Control Register, 9-8
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*/
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#define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */
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#define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */
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#define SCCR_DFBRG_SHIFT 0
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#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */
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#define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */
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#define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */
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#define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */
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/*
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* Define default values for some CCSR macros to make header files cleaner*
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*
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* To completely disable CCSR relocation in a board header file, define
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* CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
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* to a value that is the same as CONFIG_SYS_CCSRBAR.
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*/
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#ifdef CONFIG_SYS_CCSRBAR_PHYS
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#error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly. Use \
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CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
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#endif
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#ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
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#undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
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#undef CONFIG_SYS_CCSRBAR_PHYS_LOW
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#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
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#endif
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#ifndef CONFIG_SYS_CCSRBAR
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#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
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#endif
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#ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
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#else
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#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
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#endif
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#endif
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#ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
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#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
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#endif
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#define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
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CONFIG_SYS_CCSRBAR_PHYS_LOW)
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#ifndef CONFIG_SYS_IMMR
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#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
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#endif
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#endif /* __MPC85xx_H__ */
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