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https://github.com/brain-hackers/u-boot-brain
synced 2024-07-13 06:36:16 +09:00
ddf49cbf35
Devicetree files in RK3399 platform is synced from Linux, like other platforms does. Apart from these u-boot in rk3399 would also require some u-boot specific node like dmc. dmc node has big chunk of DDR timing parameters which are specific to specific board, and maintained with rk3399-sdram*.dtsi. So, create board specific -u-boot.dtsi files and move these sdram dtsi files accordingly. This would help of maintain u-boot specific changes separately without touching Linux dts(i) files which indeed easy for syncing from Linux between releases. These board specific -u-boot.dtsi can be extendible to add more u-boot specific nodes or properties in future. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
78 lines
1.5 KiB
Plaintext
78 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Collabora Ltd.
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
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*
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* Schematics available at https://dl.vamrs.com/products/ficus/docs/hw
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*/
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/dts-v1/;
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#include "rk3399-rock960.dtsi"
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/ {
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model = "96boards RK3399 Ficus";
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compatible = "vamrs,ficus", "rockchip,rk3399";
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chosen {
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stdout-path = "serial2:1500000n8";
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};
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clkin_gmac: external-gmac-clock {
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "clkin_gmac";
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#clock-cells = <0>;
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};
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};
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&gmac {
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assigned-clocks = <&cru SCLK_RMII_SRC>;
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assigned-clock-parents = <&clkin_gmac>;
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clock_in_out = "input";
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phy-supply = <&vcc3v3_sys>;
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phy-mode = "rgmii";
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 50000>;
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tx_delay = <0x28>;
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rx_delay = <0x11>;
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status = "okay";
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};
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&pcie0 {
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ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
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};
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&pinctrl {
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gmac {
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rgmii_sleep_pins: rgmii-sleep-pins {
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rockchip,pins =
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<3 15 RK_FUNC_GPIO &pcfg_output_low>;
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};
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};
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pcie {
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pcie_drv: pcie-drv {
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rockchip,pins =
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<1 24 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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usb2 {
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host_vbus_drv: host-vbus-drv {
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rockchip,pins =
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<4 27 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&vcc3v3_pcie {
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gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
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};
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&vcc5v0_host {
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gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
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};
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