mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
fcbcd59730
Currently, IECTRL is enabled after pin-mux settings for the low-level debugging for PH1-LD4 and PH1-sLD8. While IECTRL is disabled, input signals are pulled-down, i.e. glitch signal (Low to High transition) problem occurs if pin-mux is set up first. As a result, one invalid character is input to the UART block and the auto-boot counting is terminated immediately. The correct initialization procedure is: [1] Enable IECTRL (if IECTRL exists for the pins) [2] Set up pin-muxing [3] Deassert the reset of the hardware block Currently, the low-level debugging is working for PH1-sLD3 and PH1-Pro4, but just in case, follow the sequence for all the SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
||
|---|---|---|
| .. | ||
| cpu | ||
| dts | ||
| imx-common | ||
| include | ||
| lib | ||
| mach-at91 | ||
| mach-bcm283x | ||
| mach-davinci | ||
| mach-exynos | ||
| mach-highbank | ||
| mach-integrator | ||
| mach-keystone | ||
| mach-kirkwood | ||
| mach-mvebu | ||
| mach-orion5x | ||
| mach-rockchip | ||
| mach-socfpga | ||
| mach-tegra | ||
| mach-uniphier | ||
| mach-versatile | ||
| mach-zynq | ||
| mvebu-common | ||
| config.mk | ||
| Kconfig | ||
| Kconfig.debug | ||
| Makefile | ||