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https://github.com/brain-hackers/u-boot-brain
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c63e137014
JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
228 lines
8.3 KiB
C
228 lines
8.3 KiB
C
/*
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* Copyright 2009, 2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/processor.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <asm/fsl_law.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
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#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
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#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
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#define CONFIG_SYS_DDR_RCW_1 0x00000000
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#define CONFIG_SYS_DDR_RCW_2 0x00000000
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#define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/
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#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
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#define CONFIG_SYS_DDR_TIMING_4 0x00000000
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#define CONFIG_SYS_DDR_TIMING_5 0x00000000
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#define CONFIG_SYS_DDR_TIMING_3_400 0x00010000
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#define CONFIG_SYS_DDR_TIMING_0_400 0x00260802
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#define CONFIG_SYS_DDR_TIMING_1_400 0x39355322
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#define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca
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#define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000
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#define CONFIG_SYS_DDR_MODE_1_400 0x00480432
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#define CONFIG_SYS_DDR_MODE_2_400 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL_400 0x06180100
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#define CONFIG_SYS_DDR_TIMING_3_533 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0_533 0x00260802
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#define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432
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#define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce
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#define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000
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#define CONFIG_SYS_DDR_MODE_1_533 0x00040642
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#define CONFIG_SYS_DDR_MODE_2_533 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL_533 0x08200100
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#define CONFIG_SYS_DDR_TIMING_3_667 0x00030000
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#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802
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#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543
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#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1
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#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
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#define CONFIG_SYS_DDR_MODE_1_667 0x00040852
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#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
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#define CONFIG_SYS_DDR_TIMING_3_800 0x00040000
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#define CONFIG_SYS_DDR_TIMING_0_800 0x00770802
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#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
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#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
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#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
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#define CONFIG_SYS_DDR_MODE_1_800 0x00040852
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#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
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fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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phys_size_t fixed_sdram (void)
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{
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char buf[32];
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fsl_ddr_cfg_regs_t ddr_cfg_regs;
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size_t ddr_size;
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struct cpu_type *cpu;
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ulong ddr_freq, ddr_freq_mhz;
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cpu = gd->arch.cpu;
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/* P1020 and it's derivatives support max 32bit DDR width */
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if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
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ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
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} else {
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ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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}
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#if defined(CONFIG_SYS_RAMBOOT)
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return ddr_size;
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#endif
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ddr_freq = get_ddr_freq(0);
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ddr_freq_mhz = ddr_freq / 1000000;
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printf("Configuring DDR for %s MT/s data rate\n",
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strmhz(buf, ddr_freq));
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if(ddr_freq_mhz <= 400)
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memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
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else if(ddr_freq_mhz <= 533)
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memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
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else if(ddr_freq_mhz <= 667)
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memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
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else if(ddr_freq_mhz <= 800)
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memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
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else
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panic("Unsupported DDR data rate %s MT/s data rate\n",
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strmhz(buf, ddr_freq));
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/* P1020 and it's derivatives support max 32bit DDR width */
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if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1011) {
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ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
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ddr_cfg_regs.cs[0].bnds = 0x0000001F;
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}
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
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set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1);
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return ddr_size;
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}
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