mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
d40d69ee35
ARM CPUs can architecturally (speculatively) prefetch completely arbitrary normal memory locations, as defined by the current translation tables. The current MMU configuration for 64-bit Tegras maps an extremely large range of addresses as DRAM, well beyond the actual physical maximum DRAM window, even though U-Boot only needs access to the first 2GB of DRAM; the Tegra port of U-Boot deliberately limits itself to 2GB of RAM since some HW modules on at least some 64-bit Tegra SoCs can only access a 32-bit physical address space. This change reduces the amount of RAM mapped via the MMU to disallow the CPU from ever speculatively accessing RAM that U-Boot will definitely not access. This avoids the possibility of the HW raising SError due to accesses to always-invalid physical addresses. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
36 lines
776 B
C
36 lines
776 B
C
/*
|
|
* (C) Copyright 2014 - 2015 Xilinx, Inc.
|
|
* Michal Simek <michal.simek@xilinx.com>
|
|
* (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c)
|
|
*
|
|
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/system.h>
|
|
#include <asm/armv8/mmu.h>
|
|
|
|
static struct mm_region tegra_mem_map[] = {
|
|
{
|
|
.virt = 0x0UL,
|
|
.phys = 0x0UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
.virt = 0x80000000UL,
|
|
.phys = 0x80000000UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
/* List terminator */
|
|
0,
|
|
}
|
|
};
|
|
|
|
struct mm_region *mem_map = tegra_mem_map;
|