mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-19 03:03:22 +09:00
3dd22a37aa
This patch makes the necessary changes for making use of I2S0 channel instead of I2S1 channel on smdk board. This changes are done to maintain the uniformity to use I2S0 channel. Signed-off-by: Dani Krishna Mohan <krishna.md@samsung.com>
900 lines
24 KiB
C
900 lines
24 KiB
C
/*
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* (C) Copyright 2010 Samsung Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARM_ARCH_CLOCK_H_
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#define __ASM_ARM_ARCH_CLOCK_H_
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#ifndef __ASSEMBLY__
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struct exynos4_clock {
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unsigned char res1[0x4200];
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unsigned int src_leftbus;
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unsigned char res2[0x1fc];
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unsigned int mux_stat_leftbus;
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unsigned char res4[0xfc];
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unsigned int div_leftbus;
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unsigned char res5[0xfc];
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unsigned int div_stat_leftbus;
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unsigned char res6[0x1fc];
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unsigned int gate_ip_leftbus;
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unsigned char res7[0x1fc];
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unsigned int clkout_leftbus;
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unsigned int clkout_leftbus_div_stat;
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unsigned char res8[0x37f8];
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unsigned int src_rightbus;
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unsigned char res9[0x1fc];
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unsigned int mux_stat_rightbus;
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unsigned char res10[0xfc];
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unsigned int div_rightbus;
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unsigned char res11[0xfc];
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unsigned int div_stat_rightbus;
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unsigned char res12[0x1fc];
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unsigned int gate_ip_rightbus;
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unsigned char res13[0x1fc];
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unsigned int clkout_rightbus;
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unsigned int clkout_rightbus_div_stat;
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unsigned char res14[0x3608];
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unsigned int epll_lock;
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unsigned char res15[0xc];
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unsigned int vpll_lock;
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unsigned char res16[0xec];
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unsigned int epll_con0;
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unsigned int epll_con1;
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unsigned char res17[0x8];
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unsigned int vpll_con0;
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unsigned int vpll_con1;
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unsigned char res18[0xe8];
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unsigned int src_top0;
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unsigned int src_top1;
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unsigned char res19[0x8];
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unsigned int src_cam;
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unsigned int src_tv;
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unsigned int src_mfc;
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unsigned int src_g3d;
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unsigned int src_image;
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unsigned int src_lcd0;
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unsigned int src_lcd1;
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unsigned int src_maudio;
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unsigned int src_fsys;
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unsigned char res20[0xc];
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unsigned int src_peril0;
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unsigned int src_peril1;
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unsigned char res21[0xb8];
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unsigned int src_mask_top;
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unsigned char res22[0xc];
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unsigned int src_mask_cam;
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unsigned int src_mask_tv;
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unsigned char res23[0xc];
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unsigned int src_mask_lcd0;
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unsigned int src_mask_lcd1;
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unsigned int src_mask_maudio;
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unsigned int src_mask_fsys;
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unsigned char res24[0xc];
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unsigned int src_mask_peril0;
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unsigned int src_mask_peril1;
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unsigned char res25[0xb8];
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unsigned int mux_stat_top;
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unsigned char res26[0x14];
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unsigned int mux_stat_mfc;
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unsigned int mux_stat_g3d;
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unsigned int mux_stat_image;
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unsigned char res27[0xdc];
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unsigned int div_top;
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unsigned char res28[0xc];
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unsigned int div_cam;
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unsigned int div_tv;
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unsigned int div_mfc;
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unsigned int div_g3d;
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unsigned int div_image;
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unsigned int div_lcd0;
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unsigned int div_lcd1;
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unsigned int div_maudio;
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unsigned int div_fsys0;
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unsigned int div_fsys1;
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unsigned int div_fsys2;
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unsigned int div_fsys3;
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unsigned int div_peril0;
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unsigned int div_peril1;
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unsigned int div_peril2;
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unsigned int div_peril3;
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unsigned int div_peril4;
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unsigned int div_peril5;
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unsigned char res29[0x18];
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unsigned int div2_ratio;
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unsigned char res30[0x8c];
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unsigned int div_stat_top;
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unsigned char res31[0xc];
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unsigned int div_stat_cam;
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unsigned int div_stat_tv;
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unsigned int div_stat_mfc;
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unsigned int div_stat_g3d;
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unsigned int div_stat_image;
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unsigned int div_stat_lcd0;
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unsigned int div_stat_lcd1;
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unsigned int div_stat_maudio;
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unsigned int div_stat_fsys0;
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unsigned int div_stat_fsys1;
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unsigned int div_stat_fsys2;
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unsigned int div_stat_fsys3;
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unsigned int div_stat_peril0;
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unsigned int div_stat_peril1;
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unsigned int div_stat_peril2;
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unsigned int div_stat_peril3;
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unsigned int div_stat_peril4;
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unsigned int div_stat_peril5;
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unsigned char res32[0x18];
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unsigned int div2_stat;
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unsigned char res33[0x29c];
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unsigned int gate_ip_cam;
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unsigned int gate_ip_tv;
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unsigned int gate_ip_mfc;
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unsigned int gate_ip_g3d;
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unsigned int gate_ip_image;
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unsigned int gate_ip_lcd0;
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unsigned int gate_ip_lcd1;
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unsigned char res34[0x4];
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unsigned int gate_ip_fsys;
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unsigned char res35[0x8];
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unsigned int gate_ip_gps;
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unsigned int gate_ip_peril;
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unsigned char res36[0xc];
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unsigned int gate_ip_perir;
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unsigned char res37[0xc];
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unsigned int gate_block;
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unsigned char res38[0x8c];
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unsigned int clkout_cmu_top;
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unsigned int clkout_cmu_top_div_stat;
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unsigned char res39[0x37f8];
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unsigned int src_dmc;
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unsigned char res40[0xfc];
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unsigned int src_mask_dmc;
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unsigned char res41[0xfc];
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unsigned int mux_stat_dmc;
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unsigned char res42[0xfc];
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unsigned int div_dmc0;
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unsigned int div_dmc1;
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unsigned char res43[0xf8];
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unsigned int div_stat_dmc0;
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unsigned int div_stat_dmc1;
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unsigned char res44[0x2f8];
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unsigned int gate_ip_dmc;
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unsigned char res45[0xfc];
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unsigned int clkout_cmu_dmc;
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unsigned int clkout_cmu_dmc_div_stat;
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unsigned char res46[0x5f8];
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unsigned int dcgidx_map0;
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unsigned int dcgidx_map1;
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unsigned int dcgidx_map2;
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unsigned char res47[0x14];
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unsigned int dcgperf_map0;
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unsigned int dcgperf_map1;
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unsigned char res48[0x18];
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unsigned int dvcidx_map;
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unsigned char res49[0x1c];
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unsigned int freq_cpu;
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unsigned int freq_dpm;
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unsigned char res50[0x18];
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unsigned int dvsemclk_en;
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unsigned int maxperf;
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unsigned char res51[0x2f78];
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unsigned int apll_lock;
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unsigned char res52[0x4];
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unsigned int mpll_lock;
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unsigned char res53[0xf4];
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unsigned int apll_con0;
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unsigned int apll_con1;
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unsigned int mpll_con0;
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unsigned int mpll_con1;
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unsigned char res54[0xf0];
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unsigned int src_cpu;
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unsigned char res55[0x1fc];
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unsigned int mux_stat_cpu;
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unsigned char res56[0xfc];
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unsigned int div_cpu0;
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unsigned int div_cpu1;
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unsigned char res57[0xf8];
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unsigned int div_stat_cpu0;
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unsigned int div_stat_cpu1;
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unsigned char res58[0x3f8];
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unsigned int clkout_cmu_cpu;
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unsigned int clkout_cmu_cpu_div_stat;
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unsigned char res59[0x5f8];
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unsigned int armclk_stopctrl;
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unsigned int atclk_stopctrl;
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unsigned char res60[0x8];
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unsigned int parityfail_status;
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unsigned int parityfail_clear;
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unsigned char res61[0xe8];
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unsigned int apll_con0_l8;
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unsigned int apll_con0_l7;
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unsigned int apll_con0_l6;
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unsigned int apll_con0_l5;
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unsigned int apll_con0_l4;
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unsigned int apll_con0_l3;
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unsigned int apll_con0_l2;
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unsigned int apll_con0_l1;
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unsigned int iem_control;
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unsigned char res62[0xdc];
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unsigned int apll_con1_l8;
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unsigned int apll_con1_l7;
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unsigned int apll_con1_l6;
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unsigned int apll_con1_l5;
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unsigned int apll_con1_l4;
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unsigned int apll_con1_l3;
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unsigned int apll_con1_l2;
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unsigned int apll_con1_l1;
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unsigned char res63[0xe0];
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unsigned int div_iem_l8;
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unsigned int div_iem_l7;
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unsigned int div_iem_l6;
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unsigned int div_iem_l5;
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unsigned int div_iem_l4;
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unsigned int div_iem_l3;
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unsigned int div_iem_l2;
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unsigned int div_iem_l1;
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};
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struct exynos4x12_clock {
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unsigned char res1[0x4200];
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unsigned int src_leftbus;
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unsigned char res2[0x1fc];
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unsigned int mux_stat_leftbus;
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unsigned char res3[0xfc];
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unsigned int div_leftbus;
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unsigned char res4[0xfc];
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unsigned int div_stat_leftbus;
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unsigned char res5[0x1fc];
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unsigned int gate_ip_leftbus;
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unsigned char res6[0x12c];
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unsigned int gate_ip_image;
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unsigned char res7[0xcc];
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unsigned int clkout_leftbus;
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unsigned int clkout_leftbus_div_stat;
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unsigned char res8[0x37f8];
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unsigned int src_rightbus;
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unsigned char res9[0x1fc];
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unsigned int mux_stat_rightbus;
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unsigned char res10[0xfc];
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unsigned int div_rightbus;
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unsigned char res11[0xfc];
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unsigned int div_stat_rightbus;
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unsigned char res12[0x1fc];
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unsigned int gate_ip_rightbus;
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unsigned char res13[0x15c];
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unsigned int gate_ip_perir;
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unsigned char res14[0x9c];
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unsigned int clkout_rightbus;
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unsigned int clkout_rightbus_div_stat;
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unsigned char res15[0x3608];
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unsigned int epll_lock;
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unsigned char res16[0xc];
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unsigned int vpll_lock;
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unsigned char res17[0xec];
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unsigned int epll_con0;
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unsigned int epll_con1;
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unsigned int epll_con2;
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unsigned char res18[0x4];
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unsigned int vpll_con0;
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unsigned int vpll_con1;
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unsigned int vpll_con2;
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unsigned char res19[0xe4];
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unsigned int src_top0;
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unsigned int src_top1;
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unsigned char res20[0x8];
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unsigned int src_cam;
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unsigned int src_tv;
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unsigned int src_mfc;
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unsigned int src_g3d;
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unsigned char res21[0x4];
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unsigned int src_lcd;
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unsigned int src_isp;
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unsigned int src_maudio;
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unsigned int src_fsys;
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unsigned char res22[0xc];
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unsigned int src_peril0;
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unsigned int src_peril1;
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unsigned int src_cam1;
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unsigned char res23[0xb4];
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unsigned int src_mask_top;
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unsigned char res24[0xc];
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unsigned int src_mask_cam;
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unsigned int src_mask_tv;
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unsigned char res25[0xc];
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unsigned int src_mask_lcd;
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unsigned int src_mask_isp;
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unsigned int src_mask_maudio;
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unsigned int src_mask_fsys;
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unsigned char res26[0xc];
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unsigned int src_mask_peril0;
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unsigned int src_mask_peril1;
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unsigned char res27[0xb8];
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unsigned int mux_stat_top0;
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unsigned int mux_stat_top1;
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unsigned char res28[0x10];
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unsigned int mux_stat_mfc;
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unsigned int mux_stat_g3d;
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unsigned char res29[0x28];
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unsigned int mux_stat_cam1;
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unsigned char res30[0xb4];
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unsigned int div_top;
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unsigned char res31[0xc];
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unsigned int div_cam;
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unsigned int div_tv;
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unsigned int div_mfc;
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unsigned int div_g3d;
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unsigned char res32[0x4];
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unsigned int div_lcd;
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unsigned int div_isp;
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unsigned int div_maudio;
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unsigned int div_fsys0;
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unsigned int div_fsys1;
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unsigned int div_fsys2;
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unsigned int div_fsys3;
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unsigned int div_peril0;
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unsigned int div_peril1;
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unsigned int div_peril2;
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unsigned int div_peril3;
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unsigned int div_peril4;
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unsigned int div_peril5;
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unsigned int div_cam1;
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unsigned char res33[0x14];
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unsigned int div2_ratio;
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unsigned char res34[0x8c];
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unsigned int div_stat_top;
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unsigned char res35[0xc];
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unsigned int div_stat_cam;
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unsigned int div_stat_tv;
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unsigned int div_stat_mfc;
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unsigned int div_stat_g3d;
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unsigned char res36[0x4];
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unsigned int div_stat_lcd;
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unsigned int div_stat_isp;
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unsigned int div_stat_maudio;
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unsigned int div_stat_fsys0;
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unsigned int div_stat_fsys1;
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unsigned int div_stat_fsys2;
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unsigned int div_stat_fsys3;
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unsigned int div_stat_peril0;
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unsigned int div_stat_peril1;
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unsigned int div_stat_peril2;
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unsigned int div_stat_peril3;
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unsigned int div_stat_peril4;
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unsigned int div_stat_peril5;
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unsigned int div_stat_cam1;
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unsigned char res37[0x14];
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unsigned int div2_stat;
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unsigned char res38[0x29c];
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unsigned int gate_ip_cam;
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unsigned int gate_ip_tv;
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unsigned int gate_ip_mfc;
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unsigned int gate_ip_g3d;
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unsigned char res39[0x4];
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unsigned int gate_ip_lcd;
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unsigned int gate_ip_isp;
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unsigned char res40[0x4];
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unsigned int gate_ip_fsys;
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unsigned char res41[0x8];
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unsigned int gate_ip_gps;
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unsigned int gate_ip_peril;
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unsigned char res42[0xc];
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unsigned char res43[0x4];
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unsigned char res44[0xc];
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unsigned int gate_block;
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unsigned char res45[0x8c];
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unsigned int clkout_cmu_top;
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unsigned int clkout_cmu_top_div_stat;
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unsigned char res46[0x3600];
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unsigned int mpll_lock;
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unsigned char res47[0xfc];
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unsigned int mpll_con0;
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unsigned int mpll_con1;
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unsigned char res48[0xf0];
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unsigned int src_dmc;
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unsigned char res49[0xfc];
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unsigned int src_mask_dmc;
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unsigned char res50[0xfc];
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unsigned int mux_stat_dmc;
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unsigned char res51[0xfc];
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unsigned int div_dmc0;
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unsigned int div_dmc1;
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unsigned char res52[0xf8];
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unsigned int div_stat_dmc0;
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unsigned int div_stat_dmc1;
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unsigned char res53[0xf8];
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unsigned int gate_bus_dmc0;
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unsigned int gate_bus_dmc1;
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unsigned char res54[0x1f8];
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unsigned int gate_ip_dmc0;
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unsigned int gate_ip_dmc1;
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unsigned char res55[0xf8];
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unsigned int clkout_cmu_dmc;
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unsigned int clkout_cmu_dmc_div_stat;
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unsigned char res56[0x5f8];
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unsigned int dcgidx_map0;
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unsigned int dcgidx_map1;
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unsigned int dcgidx_map2;
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unsigned char res57[0x14];
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unsigned int dcgperf_map0;
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unsigned int dcgperf_map1;
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unsigned char res58[0x18];
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unsigned int dvcidx_map;
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unsigned char res59[0x1c];
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unsigned int freq_cpu;
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unsigned int freq_dpm;
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unsigned char res60[0x18];
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unsigned int dvsemclk_en;
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unsigned int maxperf;
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unsigned char res61[0x8];
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unsigned int dmc_freq_ctrl;
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unsigned int dmc_pause_ctrl;
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unsigned int dddrphy_lock_ctrl;
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unsigned int c2c_state;
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unsigned char res62[0x2f60];
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unsigned int apll_lock;
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unsigned char res63[0x8];
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unsigned char res64[0xf4];
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unsigned int apll_con0;
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unsigned int apll_con1;
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unsigned char res65[0xf8];
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unsigned int src_cpu;
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unsigned char res66[0x1fc];
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unsigned int mux_stat_cpu;
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unsigned char res67[0xfc];
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unsigned int div_cpu0;
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unsigned int div_cpu1;
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unsigned char res68[0xf8];
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unsigned int div_stat_cpu0;
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unsigned int div_stat_cpu1;
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unsigned char res69[0x2f8];
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unsigned int clk_gate_ip_cpu;
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unsigned char res70[0xfc];
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unsigned int clkout_cmu_cpu;
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unsigned int clkout_cmu_cpu_div_stat;
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unsigned char res71[0x5f8];
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unsigned int armclk_stopctrl;
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unsigned int atclk_stopctrl;
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unsigned char res72[0x10];
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unsigned char res73[0x8];
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unsigned int pwr_ctrl;
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unsigned int pwr_ctrl2;
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unsigned char res74[0xd8];
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unsigned int apll_con0_l8;
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unsigned int apll_con0_l7;
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unsigned int apll_con0_l6;
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unsigned int apll_con0_l5;
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unsigned int apll_con0_l4;
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unsigned int apll_con0_l3;
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unsigned int apll_con0_l2;
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unsigned int apll_con0_l1;
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unsigned int iem_control;
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unsigned char res75[0xdc];
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unsigned int apll_con1_l8;
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unsigned int apll_con1_l7;
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unsigned int apll_con1_l6;
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unsigned int apll_con1_l5;
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unsigned int apll_con1_l4;
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unsigned int apll_con1_l3;
|
|
unsigned int apll_con1_l2;
|
|
unsigned int apll_con1_l1;
|
|
unsigned char res76[0xe0];
|
|
unsigned int div_iem_l8;
|
|
unsigned int div_iem_l7;
|
|
unsigned int div_iem_l6;
|
|
unsigned int div_iem_l5;
|
|
unsigned int div_iem_l4;
|
|
unsigned int div_iem_l3;
|
|
unsigned int div_iem_l2;
|
|
unsigned int div_iem_l1;
|
|
unsigned char res77[0xe0];
|
|
unsigned int l2_status;
|
|
unsigned char res78[0xc];
|
|
unsigned int cpu_status;
|
|
unsigned char res79[0xc];
|
|
unsigned int ptm_status;
|
|
unsigned char res80[0x2edc];
|
|
unsigned int div_isp0;
|
|
unsigned int div_isp1;
|
|
unsigned char res81[0xf8];
|
|
unsigned int div_stat_isp0;
|
|
unsigned int div_stat_isp1;
|
|
unsigned char res82[0x3f8];
|
|
unsigned int gate_ip_isp0;
|
|
unsigned int gate_ip_isp1;
|
|
unsigned char res83[0x1f8];
|
|
unsigned int clkout_cmu_isp;
|
|
unsigned int clkout_cmu_ispd_div_stat;
|
|
unsigned char res84[0xf8];
|
|
unsigned int cmu_isp_spar0;
|
|
unsigned int cmu_isp_spar1;
|
|
unsigned int cmu_isp_spar2;
|
|
unsigned int cmu_isp_spar3;
|
|
};
|
|
|
|
struct exynos5_clock {
|
|
unsigned int apll_lock;
|
|
unsigned char res1[0xfc];
|
|
unsigned int apll_con0;
|
|
unsigned int apll_con1;
|
|
unsigned char res2[0xf8];
|
|
unsigned int src_cpu;
|
|
unsigned char res3[0x1fc];
|
|
unsigned int mux_stat_cpu;
|
|
unsigned char res4[0xfc];
|
|
unsigned int div_cpu0;
|
|
unsigned int div_cpu1;
|
|
unsigned char res5[0xf8];
|
|
unsigned int div_stat_cpu0;
|
|
unsigned int div_stat_cpu1;
|
|
unsigned char res6[0x1f8];
|
|
unsigned int gate_sclk_cpu;
|
|
unsigned char res7[0x1fc];
|
|
unsigned int clkout_cmu_cpu;
|
|
unsigned int clkout_cmu_cpu_div_stat;
|
|
unsigned char res8[0x5f8];
|
|
unsigned int armclk_stopctrl;
|
|
unsigned char res9[0x0c];
|
|
unsigned int parityfail_status;
|
|
unsigned int parityfail_clear;
|
|
unsigned char res10[0x8];
|
|
unsigned int pwr_ctrl;
|
|
unsigned int pwr_ctr2;
|
|
unsigned char res11[0xd8];
|
|
unsigned int apll_con0_l8;
|
|
unsigned int apll_con0_l7;
|
|
unsigned int apll_con0_l6;
|
|
unsigned int apll_con0_l5;
|
|
unsigned int apll_con0_l4;
|
|
unsigned int apll_con0_l3;
|
|
unsigned int apll_con0_l2;
|
|
unsigned int apll_con0_l1;
|
|
unsigned int iem_control;
|
|
unsigned char res12[0xdc];
|
|
unsigned int apll_con1_l8;
|
|
unsigned int apll_con1_l7;
|
|
unsigned int apll_con1_l6;
|
|
unsigned int apll_con1_l5;
|
|
unsigned int apll_con1_l4;
|
|
unsigned int apll_con1_l3;
|
|
unsigned int apll_con1_l2;
|
|
unsigned int apll_con1_l1;
|
|
unsigned char res13[0xe0];
|
|
unsigned int div_iem_l8;
|
|
unsigned int div_iem_l7;
|
|
unsigned int div_iem_l6;
|
|
unsigned int div_iem_l5;
|
|
unsigned int div_iem_l4;
|
|
unsigned int div_iem_l3;
|
|
unsigned int div_iem_l2;
|
|
unsigned int div_iem_l1;
|
|
unsigned char res14[0x2ce0];
|
|
unsigned int mpll_lock;
|
|
unsigned char res15[0xfc];
|
|
unsigned int mpll_con0;
|
|
unsigned int mpll_con1;
|
|
unsigned char res16[0xf8];
|
|
unsigned int src_core0;
|
|
unsigned int src_core1;
|
|
unsigned char res17[0xf8];
|
|
unsigned int src_mask_core;
|
|
unsigned char res18[0x100];
|
|
unsigned int mux_stat_core1;
|
|
unsigned char res19[0xf8];
|
|
unsigned int div_core0;
|
|
unsigned int div_core1;
|
|
unsigned int div_sysrgt;
|
|
unsigned char res20[0xf4];
|
|
unsigned int div_stat_core0;
|
|
unsigned int div_stat_core1;
|
|
unsigned int div_stat_sysrgt;
|
|
unsigned char res21[0x2f4];
|
|
unsigned int gate_ip_core;
|
|
unsigned int gate_ip_sysrgt;
|
|
unsigned char res22[0x8];
|
|
unsigned int c2c_monitor;
|
|
unsigned char res23[0xec];
|
|
unsigned int clkout_cmu_core;
|
|
unsigned int clkout_cmu_core_div_stat;
|
|
unsigned char res24[0x5f8];
|
|
unsigned int dcgidx_map0;
|
|
unsigned int dcgidx_map1;
|
|
unsigned int dcgidx_map2;
|
|
unsigned char res25[0x14];
|
|
unsigned int dcgperf_map0;
|
|
unsigned int dcgperf_map1;
|
|
unsigned char res26[0x18];
|
|
unsigned int dvcidx_map;
|
|
unsigned char res27[0x1c];
|
|
unsigned int freq_cpu;
|
|
unsigned int freq_dpm;
|
|
unsigned char res28[0x18];
|
|
unsigned int dvsemclk_en;
|
|
unsigned int maxperf;
|
|
unsigned char res29[0xf78];
|
|
unsigned int c2c_config;
|
|
unsigned char res30[0x24fc];
|
|
unsigned int div_acp;
|
|
unsigned char res31[0xfc];
|
|
unsigned int div_stat_acp;
|
|
unsigned char res32[0x1fc];
|
|
unsigned int gate_ip_acp;
|
|
unsigned char res33[0xfc];
|
|
unsigned int div_syslft;
|
|
unsigned char res34[0xc];
|
|
unsigned int div_stat_syslft;
|
|
unsigned char res35[0x1c];
|
|
unsigned int gate_ip_syslft;
|
|
unsigned char res36[0xcc];
|
|
unsigned int clkout_cmu_acp;
|
|
unsigned int clkout_cmu_acp_div_stat;
|
|
unsigned char res37[0x8];
|
|
unsigned int ufmc_config;
|
|
unsigned char res38[0x38ec];
|
|
unsigned int div_isp0;
|
|
unsigned int div_isp1;
|
|
unsigned int div_isp2;
|
|
unsigned char res39[0xf4];
|
|
unsigned int div_stat_isp0;
|
|
unsigned int div_stat_isp1;
|
|
unsigned int div_stat_isp2;
|
|
unsigned char res40[0x3f4];
|
|
unsigned int gate_ip_isp0;
|
|
unsigned int gate_ip_isp1;
|
|
unsigned char res41[0xf8];
|
|
unsigned int gate_sclk_isp;
|
|
unsigned char res42[0xc];
|
|
unsigned int mcuisp_pwr_ctrl;
|
|
unsigned char res43[0xec];
|
|
unsigned int clkout_cmu_isp;
|
|
unsigned int clkout_cmu_isp_div_stat;
|
|
unsigned char res44[0x3618];
|
|
unsigned int cpll_lock;
|
|
unsigned char res45[0xc];
|
|
unsigned int epll_lock;
|
|
unsigned char res46[0xc];
|
|
unsigned int vpll_lock;
|
|
unsigned char res47[0xc];
|
|
unsigned int gpll_lock;
|
|
unsigned char res48[0xcc];
|
|
unsigned int cpll_con0;
|
|
unsigned int cpll_con1;
|
|
unsigned char res49[0x8];
|
|
unsigned int epll_con0;
|
|
unsigned int epll_con1;
|
|
unsigned int epll_con2;
|
|
unsigned char res50[0x4];
|
|
unsigned int vpll_con0;
|
|
unsigned int vpll_con1;
|
|
unsigned int vpll_con2;
|
|
unsigned char res51[0x4];
|
|
unsigned int gpll_con0;
|
|
unsigned int gpll_con1;
|
|
unsigned char res52[0xb8];
|
|
unsigned int src_top0;
|
|
unsigned int src_top1;
|
|
unsigned int src_top2;
|
|
unsigned int src_top3;
|
|
unsigned int src_gscl;
|
|
unsigned char res53[0x8];
|
|
unsigned int src_disp1_0;
|
|
unsigned char res54[0x10];
|
|
unsigned int src_mau;
|
|
unsigned int src_fsys;
|
|
unsigned int src_gen;
|
|
unsigned char res55[0x4];
|
|
unsigned int src_peric0;
|
|
unsigned int src_peric1;
|
|
unsigned char res56[0x18];
|
|
unsigned int sclk_src_isp;
|
|
unsigned char res57[0x9c];
|
|
unsigned int src_mask_top;
|
|
unsigned char res58[0xc];
|
|
unsigned int src_mask_gscl;
|
|
unsigned char res59[0x8];
|
|
unsigned int src_mask_disp1_0;
|
|
unsigned char res60[0x4];
|
|
unsigned int src_mask_mau;
|
|
unsigned char res61[0x8];
|
|
unsigned int src_mask_fsys;
|
|
unsigned int src_mask_gen;
|
|
unsigned char res62[0x8];
|
|
unsigned int src_mask_peric0;
|
|
unsigned int src_mask_peric1;
|
|
unsigned char res63[0x18];
|
|
unsigned int src_mask_isp;
|
|
unsigned char res67[0x9c];
|
|
unsigned int mux_stat_top0;
|
|
unsigned int mux_stat_top1;
|
|
unsigned int mux_stat_top2;
|
|
unsigned int mux_stat_top3;
|
|
unsigned char res68[0xf0];
|
|
unsigned int div_top0;
|
|
unsigned int div_top1;
|
|
unsigned char res69[0x8];
|
|
unsigned int div_gscl;
|
|
unsigned char res70[0x8];
|
|
unsigned int div_disp1_0;
|
|
unsigned char res71[0xc];
|
|
unsigned int div_gen;
|
|
unsigned char res72[0x4];
|
|
unsigned int div_mau;
|
|
unsigned int div_fsys0;
|
|
unsigned int div_fsys1;
|
|
unsigned int div_fsys2;
|
|
unsigned char res73[0x4];
|
|
unsigned int div_peric0;
|
|
unsigned int div_peric1;
|
|
unsigned int div_peric2;
|
|
unsigned int div_peric3;
|
|
unsigned int div_peric4;
|
|
unsigned int div_peric5;
|
|
unsigned char res74[0x10];
|
|
unsigned int sclk_div_isp;
|
|
unsigned char res75[0xc];
|
|
unsigned int div2_ratio0;
|
|
unsigned int div2_ratio1;
|
|
unsigned char res76[0x8];
|
|
unsigned int div4_ratio;
|
|
unsigned char res77[0x6c];
|
|
unsigned int div_stat_top0;
|
|
unsigned int div_stat_top1;
|
|
unsigned char res78[0x8];
|
|
unsigned int div_stat_gscl;
|
|
unsigned char res79[0x8];
|
|
unsigned int div_stat_disp1_0;
|
|
unsigned char res80[0xc];
|
|
unsigned int div_stat_gen;
|
|
unsigned char res81[0x4];
|
|
unsigned int div_stat_mau;
|
|
unsigned int div_stat_fsys0;
|
|
unsigned int div_stat_fsys1;
|
|
unsigned int div_stat_fsys2;
|
|
unsigned char res82[0x4];
|
|
unsigned int div_stat_peric0;
|
|
unsigned int div_stat_peric1;
|
|
unsigned int div_stat_peric2;
|
|
unsigned int div_stat_peric3;
|
|
unsigned int div_stat_peric4;
|
|
unsigned int div_stat_peric5;
|
|
unsigned char res83[0x10];
|
|
unsigned int sclk_div_stat_isp;
|
|
unsigned char res84[0xc];
|
|
unsigned int div2_stat0;
|
|
unsigned int div2_stat1;
|
|
unsigned char res85[0x8];
|
|
unsigned int div4_stat;
|
|
unsigned char res86[0x184];
|
|
unsigned int gate_top_sclk_disp1;
|
|
unsigned int gate_top_sclk_gen;
|
|
unsigned char res87[0xc];
|
|
unsigned int gate_top_sclk_mau;
|
|
unsigned int gate_top_sclk_fsys;
|
|
unsigned char res88[0xc];
|
|
unsigned int gate_top_sclk_peric;
|
|
unsigned char res89[0x1c];
|
|
unsigned int gate_top_sclk_isp;
|
|
unsigned char res90[0xac];
|
|
unsigned int gate_ip_gscl;
|
|
unsigned char res91[0x4];
|
|
unsigned int gate_ip_disp1;
|
|
unsigned int gate_ip_mfc;
|
|
unsigned int gate_ip_g3d;
|
|
unsigned int gate_ip_gen;
|
|
unsigned char res92[0xc];
|
|
unsigned int gate_ip_fsys;
|
|
unsigned char res93[0x8];
|
|
unsigned int gate_ip_peric;
|
|
unsigned char res94[0xc];
|
|
unsigned int gate_ip_peris;
|
|
unsigned char res95[0x1c];
|
|
unsigned int gate_block;
|
|
unsigned char res96[0x1c];
|
|
unsigned int mcuiop_pwr_ctrl;
|
|
unsigned char res97[0x5c];
|
|
unsigned int clkout_cmu_top;
|
|
unsigned int clkout_cmu_top_div_stat;
|
|
unsigned char res98[0x37f8];
|
|
unsigned int src_lex;
|
|
unsigned char res99[0x1fc];
|
|
unsigned int mux_stat_lex;
|
|
unsigned char res100[0xfc];
|
|
unsigned int div_lex;
|
|
unsigned char res101[0xfc];
|
|
unsigned int div_stat_lex;
|
|
unsigned char res102[0x1fc];
|
|
unsigned int gate_ip_lex;
|
|
unsigned char res103[0x1fc];
|
|
unsigned int clkout_cmu_lex;
|
|
unsigned int clkout_cmu_lex_div_stat;
|
|
unsigned char res104[0x3af8];
|
|
unsigned int div_r0x;
|
|
unsigned char res105[0xfc];
|
|
unsigned int div_stat_r0x;
|
|
unsigned char res106[0x1fc];
|
|
unsigned int gate_ip_r0x;
|
|
unsigned char res107[0x1fc];
|
|
unsigned int clkout_cmu_r0x;
|
|
unsigned int clkout_cmu_r0x_div_stat;
|
|
unsigned char res108[0x3af8];
|
|
unsigned int div_r1x;
|
|
unsigned char res109[0xfc];
|
|
unsigned int div_stat_r1x;
|
|
unsigned char res110[0x1fc];
|
|
unsigned int gate_ip_r1x;
|
|
unsigned char res111[0x1fc];
|
|
unsigned int clkout_cmu_r1x;
|
|
unsigned int clkout_cmu_r1x_div_stat;
|
|
unsigned char res112[0x3608];
|
|
unsigned int bpll_lock;
|
|
unsigned char res113[0xfc];
|
|
unsigned int bpll_con0;
|
|
unsigned int bpll_con1;
|
|
unsigned char res114[0xe8];
|
|
unsigned int src_cdrex;
|
|
unsigned char res115[0x1fc];
|
|
unsigned int mux_stat_cdrex;
|
|
unsigned char res116[0xfc];
|
|
unsigned int div_cdrex;
|
|
unsigned char res117[0xfc];
|
|
unsigned int div_stat_cdrex;
|
|
unsigned char res118[0x2fc];
|
|
unsigned int gate_ip_cdrex;
|
|
unsigned char res119[0x10];
|
|
unsigned int dmc_freq_ctrl;
|
|
unsigned char res120[0x4];
|
|
unsigned int drex2_pause;
|
|
unsigned char res121[0xe0];
|
|
unsigned int clkout_cmu_cdrex;
|
|
unsigned int clkout_cmu_cdrex_div_stat;
|
|
unsigned char res122[0x8];
|
|
unsigned int lpddr3phy_ctrl;
|
|
unsigned int lpddr3phy_con0;
|
|
unsigned int lpddr3phy_con1;
|
|
unsigned int lpddr3phy_con2;
|
|
unsigned int lpddr3phy_con3;
|
|
unsigned int pll_div2_sel;
|
|
unsigned char res123[0xf5d8];
|
|
};
|
|
|
|
/* structure for epll configuration used in audio clock configuration */
|
|
struct set_epll_con_val {
|
|
unsigned int freq_out; /* frequency out */
|
|
unsigned int en_lock_det; /* enable lock detect */
|
|
unsigned int m_div; /* m divider value */
|
|
unsigned int p_div; /* p divider value */
|
|
unsigned int s_div; /* s divider value */
|
|
unsigned int k_dsm; /* k value of delta signal modulator */
|
|
};
|
|
#endif
|
|
|
|
#define MPLL_FOUT_SEL_SHIFT 4
|
|
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/
|
|
#define TIMEOUT_EPLL_LOCK 1000
|
|
|
|
#define AUDIO_0_RATIO_MASK 0x0f
|
|
#define AUDIO_1_RATIO_MASK 0x0f
|
|
|
|
#define AUDIO0_SEL_MASK 0xf
|
|
#define AUDIO1_SEL_MASK 0xf
|
|
|
|
#define CLK_SRC_SCLK_EPLL 0x7
|
|
#define CLK_SRC_MOUT_EPLL (1<<12)
|
|
#define AUDIO_CLKMUX_ASS (1<<0)
|
|
|
|
/* CON0 bit-fields */
|
|
#define EPLL_CON0_MDIV_MASK 0x1ff
|
|
#define EPLL_CON0_PDIV_MASK 0x3f
|
|
#define EPLL_CON0_SDIV_MASK 0x7
|
|
#define EPLL_CON0_MDIV_SHIFT 16
|
|
#define EPLL_CON0_PDIV_SHIFT 8
|
|
#define EPLL_CON0_SDIV_SHIFT 0
|
|
#define EPLL_CON0_LOCK_DET_EN_SHIFT 28
|
|
#define EPLL_CON0_LOCK_DET_EN_MASK 1
|
|
|
|
#define MPLL_FOUT_SEL_MASK 0x1
|
|
#define BPLL_FOUT_SEL_SHIFT 0
|
|
#define BPLL_FOUT_SEL_MASK 0x1
|
|
#endif
|