mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
113 lines
3.3 KiB
C
113 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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* Keith Outwater, keith_outwater@mvis.com
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*/
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#ifndef _VIRTEX2_H_
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#define _VIRTEX2_H_
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#include <xilinx.h>
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/*
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* Slave SelectMap Implementation function table.
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*/
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typedef struct {
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xilinx_pre_fn pre;
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xilinx_pgm_fn pgm;
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xilinx_init_fn init;
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xilinx_err_fn err;
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xilinx_done_fn done;
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xilinx_clk_fn clk;
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xilinx_cs_fn cs;
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xilinx_wr_fn wr;
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xilinx_rdata_fn rdata;
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xilinx_wdata_fn wdata;
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xilinx_busy_fn busy;
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xilinx_abort_fn abort;
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xilinx_post_fn post;
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} xilinx_virtex2_slave_selectmap_fns;
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/* Slave Serial Implementation function table */
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typedef struct {
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xilinx_pgm_fn pgm;
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xilinx_clk_fn clk;
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xilinx_rdata_fn rdata;
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xilinx_wdata_fn wdata;
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} xilinx_virtex2_slave_serial_fns;
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#if defined(CONFIG_FPGA_VIRTEX2)
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extern struct xilinx_fpga_op virtex2_op;
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# define FPGA_VIRTEX2_OPS &virtex2_op
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#else
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# define FPGA_VIRTEX2_OPS NULL
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#endif
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/* Device Image Sizes (in bytes)
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*********************************************************************/
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#define XILINX_XC2V40_SIZE (338208 / 8)
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#define XILINX_XC2V80_SIZE (597408 / 8)
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#define XILINX_XC2V250_SIZE (1591584 / 8)
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#define XILINX_XC2V500_SIZE (2557857 / 8)
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#define XILINX_XC2V1000_SIZE (3749408 / 8)
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#define XILINX_XC2V1500_SIZE (5166240 / 8)
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#define XILINX_XC2V2000_SIZE (6808352 / 8)
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#define XILINX_XC2V3000_SIZE (9589408 / 8)
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#define XILINX_XC2V4000_SIZE (14220192 / 8)
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#define XILINX_XC2V6000_SIZE (19752096 / 8)
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#define XILINX_XC2V8000_SIZE (26185120 / 8)
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#define XILINX_XC2V10000_SIZE (33519264 / 8)
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/* Descriptor Macros
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*********************************************************************/
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#define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
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{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
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FPGA_VIRTEX2_OPS }
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#endif /* _VIRTEX2_H_ */
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